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? the advance information presented herein represents a product that is developmental or prototype. the noted characteristics are design targets. integrated device technologies, inc. (idt) reserves the right to change any circuitry or specifications without notice. 1. general description the dac1658q and the DAC1653Q are high-speed high-performance 16-bit quad channel digital-to-analog converter (dac) with high and low common-mode output. the devices provide a sample rate up to 1.50 gsps with selectable ?? , ?? and ?? interpolation filters optimized for multi-carrier and broadband wireless transmitters. when both devices are referred to in this data sheet, the following convention will be used: dac165xq. the dac165xq integrates a jesd204b high-speed serial input data interface running up to 10 gbps allowing quad channel input sampling at up to 750 msps over eight differential lanes. it offers numerous advantages over traditional parallel digital interfaces: ? easier printed-circuit board (pcb) layout ? lower radiated noise ? lower pin count ? self-synchronous link ? skew compensation ? deterministic latency ? multiple device synchronization (mds); jesd204b subclass 1 support ? harmonic clocking support ? assured fpga interoperability there are two versions of the dac165xq: ? low common-mode output voltage (part identification DAC1653Q) ? high common-mode output voltage (part identification dac1658q) two optional on-chip digital modulators convert the complex i/q pattern from baseband to if. the mixer frequency is set by writing to the serial peripheral interface (spi) control registers associated with the on-chip 40-bit numerically controlled oscillator (nco). this accurately places the if carrier in the frequency domain. the 13-bit phase adjustment feature, the 12-bit digital gain and the 16-bit digital offset enable full control of the analog output signals. the dac165xq is fully compatible with device subclass 1 of the jedec jesd204b standard, guaranteeing deterministic and repeatable interface latency using the differential sysref signal. the device also supports harmonic clocking to reduce system-level clock synthesis and distribution challenges. DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface: up to 1.50 gsps; x2, x4 and x8 interpolating rev. 1.03 ? 13 may 2013 advance data sheet
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 2 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps multiple device synchronization (mds) enables multiple dac channels to be sample synchronous and phase coherent to within one dac clock period. mds is ideal for lte and lte-a mimo transceiver applications. the dac165xq includes an internal regulation to adjust the full-scale output current. the internal regulator adjusts the full-scale output current between 8.1 ma and 34 ma. the device is available in a hla72 package (10 mm ? 10 mm). it is supported by customer demo boards that are supplied with or without fpga logic devices. 2. features and benefits ? quad channel 16-bit resolution ? sfdr rbw = 85 dbc typical (f s = 1.47456 gsps; interpolation ? 2; bandwidth = 250 mhz; f out = 150 mhz) ? 1.50 gsps maximum output update rate ? nsd = ? 162 dbm/hz typical (f o = 20 mhz) ? jedec jesd204b device subclass i compatible: sysref based deterministic and repeatable interface latency ? imd3 = 85 dbc typical (f s = 1.47456 gsps; interpolation ? 2; f o1 = 152 mhz; f o2 = 153 mhz) ? multiple device synchronization (mds) enables multiple dac channels to be sample synchronous and phase coherent to within one dac clock period ? one carrier aclr = 77 db typical (f s = 1.47456 gsps; f nco = 230 mhz) ? 8 configurable jesd204b serial input lanes running up to 10 gbps with embedded termination and programmable equalization gain ? rf enable/disable pin and rf automatic mute. the rf enable feature is available via one of the io pins ? 750 msps maximum baseband input data rate ? very low noise bypassable integrated phase-locked loop (pll); no external capacitors ? spi interface (3-wire or 4-wire mode) for control setting and status monitoring ? clock divider by 2, 4, 6 or 8 available at the input of the clock path ? differential scalable output current from 8.1 ma to 34 ma ? group delay compensation ? two embedded ncos with 40-bit programmable frequency and 16-bit phase adjustment ? power-down mode control ? embedded complex (iq) digital modulator ? on-chip 0.7 v reference ? 1.2 v and 2.5 v or 3.3 v power supplies ? industrial temperature range ? 40 ? c to +85 ? c ? flexible spi power supply (1.8 v or 1.2 v) ensuring compatibility with on-board spi bus ? hla72 package (10 mm ? 10 mm) ? flexible differential signals (sync) power supply (1.8 v or 1.2 v) ensuring compatibility with on-board devices
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 3 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 3. applications ? wireless infrastructure radio base station transceivers, including: lte-a, lte, mc_gsm, w-cdma, td-scdma ? lmds/mmds, point-to-point microwave backhaul ? direct digital synthesis (dds) instruments ? high-definition video broadcast production equipment ? automated test equipment (ate) 4. ordering information table 1. ordering information type number package name description version DAC1653Q1g5naga hla72 hla 10 ? 10 ? 0.85 mm psc-4438 DAC1653Q1g25naga hla72 hla 10 ? 10 ? 0.85 mm psc-4438 DAC1653Q1g0naga hla72 hla 10 ? 10 ? 0.85 mm psc-4438 dac1658q1g5naga hla72 hla 10 ? 10 ? 0.85 mm psc-4438 dac1658q1g25naga hla72 hla 10 ? 10 ? 0.85 mm psc-4438 dac1658q1g0naga hla72 hla 10 ? 10 ? 0.85 mm psc-4438
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 4 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 5. block diagram fig 1. dac165xq block diagram ioutb_p ioutb_n iouta_p iouta_n + offset control cos sin cos sin dac b virres gapout + clip. clip. 10-bit gain control 10-bit gain control ref. bandgap and biasing dac a x2 fir 2 x2 fir 1 x2 fir 2 x2 fir 3 x2 fir 3 x2 fir 1 vin_ab_p3 vin_ab_n3 digital layer processing jesd204b spi control registers sdo sdio csb sclk reset_n sysref_w_n sysref_w_p sysref_e_n sysref_e_p vin_ab_p2 vin_ab_n2 vin_ab_p1 vin_ab_n1 vin_ab_p0 l0 l1 l2 l3 vin_ab_n0 syncb_ab_n syncb_ab_p clkin_n clkin_p inter lane alignment lane proc dac lane proc lane proc lane proc auto mute frame assembly single side band modulator 13 bits phase compensation 12 bits gains control x sin x x sin x interrupt managment/ monitoring features ioutd_p ioutd_n ioutc_p ioutc_n + offset control dac d + clip. clip. 10-bit gain control 10-bit gain control dac c x2 fir 2 x2 fir 1 x2 fir 2 x2 fir 3 x2 fir 3 x2 fir 1 vin_cd_p3 vin_cd_n3 digital layer processing jesd204b vin_cd_p2 vin_cd_n2 vin_cd_p1 vin_cd_n1 vin_cd_p0 l0 l1 l2 l3 vin_cd_n0 syncb_cd_p syncb_cd_n inter lane alignment lane proc lane proc lane proc lane proc auto mute frame assembly single side band modulator 13 bits phase compensation 12 bits gains control x sin x x sin x clock domains monitoring and synchronization clock generator unit/pll clock dividers group delay compen- sation nco_ab 40-bits frequency setting 16-bits phase adjustment nco_cd 40-bits frequency setting 16-bits phase adjustment io0 signal power detector signal power detector io1 io2 io3
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 5 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 6. pinning information 6.1 pinning 6.2 pin description v dda(out) (pins 47 and 52): dac1658q: 3.3 v. DAC1653Q: 2.5 v or 3.3 v. fig 2. dac165xq pin configuration dac165xq hla72 10 mm 10 mm (0.5 mm pitch) transparent top view syncb_cd_n v d d j ( 1 v 2 ) syncb_ab_p v ddj_so v ddd(1v2) v ddd(1v2) io3 v ddd_io io2 sdo gnd sdio io1 reset_n io0 scs_n gnd sclk v ddd(1v2) v ddd(1v2) sysref_w_n sysref_e_n sysref_w_p sysref_e_p v dda(out) v d d a ( 1 v 2 ) clkin_n vires clkin_p gapout v dda(1v2) v dda(1v2) vin_ab_n0 vin_ab_p1 vin_ab_n1 v ddj(1v2) vin_ab_p2 vin_ab_n2 vin_ab_p3 vin_ab_n3 vin_cd_p0 vin_cd_n0 vin_cd_p1 vin_cd_n1 v ddj(1v2) vin_cd_p2 vin_cd_n2 vin_cd_p3 iouta_p iouta_n v dda(1v2) v dda(1v2) ioutb_n ioutb_p v dda(1v2) v dda(out) v dda(out) v dda(1v2) ioutc_p ioutc_n v dda(1v2) v dda(1v2) ioutd_n ioutd_p syncb_ab_n syncb_cd_p v dda(out) v dda(out) vin_ab_p0 vin_cd_n3 v d d a ( 1 v 2 ) v dda(1v2) 17 18 38 37 16 39 15 40 14 41 13 42 12 43 11 44 10 45 9 46 8 47 7 48 6 49 5 50 4 51 3 52 2 1 53 54 71 72 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 20 19 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 terminal 1 index area table 2. pin description pin symbol type description 1v dda(out) p dac1658q: 3.3 v analog power supply DAC1653Q: 2.5 v or 3.3 v analog power supply 2v dda(1v2) p 1.2 v analog power supply 3 clkin_p i clock input (positive) 4 clkin_n i clock input (negative)
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 6 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 5v dda(out) p dac1658q: 3.3 v analog power supply DAC1653Q: 2.5 v or 3.3 v analog power supply 6 sysref_w_p i/o multiple devices synchronization positive signal, west side 7 sysref_w_n i/o multiple devices synchronization negative signal, west side 8v ddd(1v2) p 1.2 v digital power supply 9 gnd g ground 10 io0 i/o io port bit 0 11 io1 i/o io port bit 1 12 gnd i ground 13 io2 i/o io port bit 2 14 io3 i/o io port bit 3 15 v ddd(1v2) p 1.2 v digital power supply 16 v ddj(1v2) p 1.2 v jedec204b interface power supply 17 syncb_ab_p o jesd204b sync signal for dacs a/b (positive) 18 syncb_ab_n o jesd204b sync signal for dacs a/b (negative) 19 vin_ab_p0 i dac a/b lane 0 serial interface, positive input 20 vin_ab_n0 i dac a/b lane 0 serial interface, negative input 21 vin_ab_p1 i dac a/b lane 1 serial interface, positive input 22 vin_ab_n1 i dac a/b lane 1 serial interface, negative input 23 v ddj(1v2) p 1.2 v jedec204b interface power supply 24 vin_ab_p2 i dac a/b lane 2 serial interface, positive input 25 vin_ab_n2 i dac a/b lane 2 serial interface, negative input 26 vin_ab_p3 i dac a/b lane 3 serial interface, positive input 27 vin_ab_n3 i dac a/b lane 3 serial interface, negative input 28 vin_cd_p0 i dac c/d lane 0 serial interface, positive input 29 vin_cd_n0 i dac c/d lane 0 serial interface, negative input 30 vin_cd_p1 i dac c/d lane 1 serial interface, positive input 31 vin_cd_n1 i dac c/d lane 1 serial interface, negative input 32 v ddj(1v2) p 1.2 v jedec204b interface power supply 33 vin_cd_p2 i dac c/d lane 2 serial interface, positive input 34 vin_cd_n2 i dac c/d lane 2 serial interface, negative input 35 vin_cd_p3 i dac c/d lane 3 serial interface, positive input 36 vin_cd_n3 i dac c/d lane 3 2serial interface, negative input 37 syncb_1_p o jesd204b sync signal for dacs c/d (positive) 38 syncb_1_n o jesd204b sync signal for dacs c/d (negative) 39 v ddj_so p jedec204b sync output buffer power supply (1.2 v or 1.8 v) 40 v ddd(1v2) p 1.2 v digital power supply 41 v ddd_io p digital io power supply (1.2 v or 1.8 v) (including spi) 42 sdo o spi data output 43 sdio i/o spi data input/output table 2. pin description ?continued pin symbol type description
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 7 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 44 reset_n i general reset (active low) 45 scs_n i spi chip select (active low) 46 sclk i spi clock input 47 v ddd(1v2) p 1.2 v digital power supply 48 sysref_e_n i/o multiple devices synchronization negative signal, east side 49 sysref_e_p i/o multiple devices synchronization positive signal, east side 50 v dda(1v2) p 1.2 v analog power supply 51 vires i/o vi-biasing resistor 52 gapout i/o bandgap output voltage 53 v dda(1v2) p 1.2 v analog power supply 54 v dda(out) p dac1658q: 3.3 v analog power supply DAC1653Q: 2.5 v or 3.3 v analog power supply 55 v dda(1v2) p 1.2 v analog power supply 56 ioutd_p o dac d output current 57 ioutd_n o complementary dac d output current 58 v dda(1v2) p 1.2 v analog power supply 59 v dda(1v2) p 1.2 v analog power supply 60 ioutc_n o complementary dac c output current 61 ioutc_p o dac c output current 62 v dda(1v2) p 1.2 v analog power supply 63 v dda(out) p dac1658q: 3.3 v analog power supply DAC1653Q: 2.5 v or 3.3 v analog power supply 64 v dda(out) p dac1658q: 3.3 v analog power supply DAC1653Q: 2.5 v or 3.3 v analog power supply 65 v dda(1v2) p 1.2 v analog power supply 66 ioutb_p o dac b output current 67 ioutb_n o complementary dac b output current 68 v dda(1v2) p 1.2 v analog power supply 69 v dda(1v2) p 1.2 v analog power supply 70 iouta_n o complementary dac a output current 71 iouta_p o dac a output current 72 v dda(1v2) p 1.2 v analog power supply table 2. pin description ?continued pin symbol type description
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 8 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 7. limiting values 8. thermal characteristics [1] in compliance with jedec test board; in free air with 64 thermal vias, class 5. [2] in free air with 64 thermal vias, class 5. table 3. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dda(out) analog output supply voltage dac1658q: 3.3 v ? 0.5 +4.6 v DAC1653Q: 2.5 v or 3.3 v ? 0.5 +4.6 v v ddd(1v2) digital supply voltage (1.2 v) ? 0.5 +1.5 v v dda(1v2) analog supply voltage (1.2 v) ? 0.5 +1.5 v v i input voltage input pins referenced to gnd ? 0.5 v v o output voltage pins iouta_p, iouta_n, ioutb_p, ioutb_n, ioutc_p, ioutc_n, ioutd_p, ioutd_n; io0; io1; io2; io3; referenced to gnd ? 0.5 +4.6 v v ddd(io) i/o digital supply voltage pins sdo, sdio,sclk, scs_n, reset_n, jtag, io0, rf_enable/io1 ? 0.5 2.1 v v ddd(so) differential sync voltage pins sync_ab_p/n and sync_cd_p/n ? 0.5 2.1 v t stg storage temperature ? 55 +150 ? c t amb ambient temperature ? 40 +85 ? c t j junction temperature ? 40 +125 ? c table 4. thermal characteristics symbol parameter conditions typ unit jedec 4l board r th(j-a) thermal resistance from junction to ambient [1] k/w r th(j-c) thermal resistance from junction to case [1] k/w application board r th(j-a) thermal resistance from junction to ambient 6 layers [2] k/w 8 layers [2] k/w 12 layers [2] k/w
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 9 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 9. static characteristics 9.1 common characteristics table 5. characteristics v dda(1v2) = 1.2 v; v ddd(1v2) = 1.2 v; typical values measured at t amb = +25 ? c; r l = 50 ? ; i o(fs) = 20 ma; maximum sample rate used; external pll; no inverse (sinus x) / x; no output correction; output level = 1 v (p-p); unless otherwise specified. symbol parameter conditions test [1] min typ max unit v dda analog supply voltage (3.3 v) dac1658q: 3.3 v c 3.15 3.3 3.45 v DAC1653Q: 2.5 v or 3.3 v c 2.38 2.5 or 3.3 3.45 v v ddd(1v2) digital supply voltage (1.2 v) c 1.14 1.2 1.26 v v dda(1v2) analog supply voltage (1.2 v c 1.1 1.2 1.3 v v ddd(io) i/o digital supply voltage 1.2 v or 1.8 v for ios and spi signals c 1.14 1.2 2.1 v c 1.14 1.8 2.1 v v ddd(so) differential digital supply voltage c 1.14 1.2 2.1 v c 1.14 1.8 2.1 v clock inputs (pins clkin_p, clkin_n) v i input voltage |v gpd | < 50 mv c [2] 825 - mv v idth input differential threshold voltage |v gpd | < 50 mv c [2] ? 100 - +100 mv r i input resistance d - 100 - ? c i input capacitance d - - pf digital inputs/outputs (sysref_w_p/sysref_w_n, sysref_e_p/sysref_e_n) v i input voltage |v gpd | < 50 mv c [2] 825 - mv v idth input differential threshold voltage |v gpd | < 50 mv c [2] ? 100 - +100 mv r i input resistance d - 100 - ? c i input capacitance d - - pf digital inputs (pins sdo, sdio, sclk, scs_n, reset_n, io0, io1, io2, io3) v il low-level input voltage c gnd - 0.3v ddd(io) v v ih high-level input voltage c 0.7v ddd(io) -v ddd(io) v digital inputs (vinx_p/vinx_n) following the lv-oif-11g-sr; cml format v cm common-mode voltage ac coupling is mandatory; controlled by spi register c 0.580 - 1.126 v
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 10 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps v pp-diff differential peak-to-peak voltage at 6 gbps c 80 - - mv at 7.5 gbps c 80 - - mv at 10 gbps c 110 - - mv z diff differential impedance controlled by spi register i 71 100 190 ? hi-z diff tri-state observed impendance d- 64- k ? dr data rate d 1 - 10 gbps digital outputs (pins sync_out_p and sync_out_n) v cm common-mode voltage controlled by spi register - v ddddif = 1.8 v d 1.0 - 1.7 v v ddddif = 1.3 v d 0.4 - 1.2 v v ddddif = 1.2 v d 0.4 - 1.1 v v o(diff)(swing) swing differential output voltage d 100 - 1200 mv digital outputs (pins sdo, sdio) v ol low-level output voltage c - - 0.3v dddio v v oh high-level output voltage c 0.7v dddio -- v reference voltage output (pin gapout) v o(ref) reference output voltage t amb = 25 ? c i - 0.70 - v i o(ref) reference output current external voltage = 0.70 v d - - ? a ? v o(ref) reference output voltage variation d - - ppm/ ? c analog auxiliary outputs (only for DAC1653Q: connected internally to the outputs pins outx_p/outx_n) i o(fs) full-scale output current auxiliary dacs; differential inputs (normal resolution) i - 4.4 - ma auxiliary dacs; differential inputs (high resolution) i - 77.2 - a v o(aux) auxiliary output voltage c0 - 2 v n dac(aux)mono auxiliary dac monotonicity guaranteed d - 10 - bits table 5. characteristics ?continued v dda(1v2) = 1.2 v; v ddd(1v2) = 1.2 v; typical values measured at t amb = +25 ? c; r l = 50 ? ; i o(fs) = 20 ma; maximum sample rate used; external pll; no inverse (sinus x) / x; no output correction; output level = 1 v (p-p); unless otherwise specified. symbol parameter conditions test [1] min typ max unit
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 11 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps [1] d = guaranteed by design; c = guaranteed by characterization; i = 100 % industrially tested. [2] |v gpd | represents the ground potential difference voltage. this is the voltage that results from current flowing through the finite resistance and the inductance between the receiver and the driver circuit ground voltages. dac output timing f s sampling rate dac165xq1g5 c - - 1500 msps dac165xq1g25 c - - 1250 msps dac165xq1g0 c - - 1000 msps t s settling time to = ? 0.5lsb d - 20 - ns table 5. characteristics ?continued v dda(1v2) = 1.2 v; v ddd(1v2) = 1.2 v; typical values measured at t amb = +25 ? c; r l = 50 ? ; i o(fs) = 20 ma; maximum sample rate used; external pll; no inverse (sinus x) / x; no output correction; output level = 1 v (p-p); unless otherwise specified. symbol parameter conditions test [1] min typ max unit
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 12 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 9.2 specific characteristics table 6. specific characteristics v dda1v2 = 1.2 v; v ddd1v2 = 1.2 v; typical values measured at t amb = +25 ? c; r l = 50 ? ; i o(fs) = 20 ma; maximum sample rate used; no inverse (sinus x) / x; no output correction; output level = 1 v (p-p); unless otherwise specified. symbol parameter conditions test dac1658q: high common-mode DAC1653Q: low common-mode unit min typ max min typ max currents i dda analog supply current (3.3 v) all use cases c - 126 - - 246 - ma i ddd(io) digital supply current for io pins link to spi io0/io1/io2/io3 activity c - 2 - - 2 - ma i ddd(sync) digital supply current for sync pins v ddd(diff) = 1.2 v c - 22 - - 22 - ma v ddd(diff) = 1.8 v c - 38 - - 38 - ma i ddd digital supply current nco off; ? 2 interpolation;; mds off; invsinc off, phase correction off f s = 983.04 msps c - 394 - - 394 - ma f s = 1228.8 msps c - - - - ma f s = 1474.56 msps c - 548 - - 548 - ma f s = 1760.00 msps c - - - - ma nco on at 150 mhz; ? 2 interpolation;; mds off; invsinc off, phase correction on f s = 983.04 msps c - - - - ma f s = 1228.8 msps c - - - - ma f s = 1474.56 msps c - 680 - - 680 - ma f s = 1760.00 msps c - - - - ma i dda(1v2) analog supply current v dda(1v2) = 1.2 v c - 412 - - 412 - ma
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 13 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps power p tot total power dissipation nco off; ? 2 interpolation;; mds off; invsinc off, phase correction off v dda = 3.3 v; all v ddd = 1.2 v f s = 983.04 msps; eight jesd204b lanes at 4.9152 gbps c - 1486 - - 1982 - mw f s = 1228.8 msps; eight jesd204b lanes at 6.144 gbps c - - - - mw f s = 1474.56 msps; eight jesd204b lanes at 7.3728 gbps c - 1770 - - 2166 - mw v dda = 2.5 v; all v ddd = 1.2 v f s = 983.04 msps; eight jesd204b lanes at 4.9152 gbps c n.a. - 1786 - mw f s = 1228.8 msps; eight jesd204b lanes at 6.144 gbps c n.a. - - mw f s = 1474.56 msps; eight jesd204b lanes at 7.3728 gbps c n.a. - 1970 - mw full power-down c - 12 - - 12 - mw analog outputs (pins iouta_p, iouta_n, ioutb_p, ioutb_n) i o(fs) full-scale output current d 8.1 - 34 8.1 - 34 ma i o(dc) dc output current this dc offset is to be taken into account into filter design and component connection d- 4 - - 4 -ma table 6. specific characteristics ?continued v dda1v2 = 1.2 v; v ddd1v2 = 1.2 v; typical values measured at t amb = +25 ? c; r l = 50 ? ; i o(fs) = 20 ma; maximum sample rate used; no inverse (sinus x) / x; no output correction; output level = 1 v (p-p); unless otherwise specified. symbol parameter conditions test dac1658q: high common-mode DAC1653Q: low common-mode unit min typ max min typ max
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 14 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps [1] d = guaranteed by design; c = guaranteed by characterization; i = 100 % industrially tested. v o output voltage d 1.5 - v dda 0 - 1.8 v v o(cm) common-mode output voltage d 2.2 3.05 - - 0.25 - v r o output resistance d - 250 - - 250 - k ? c o differential output capacitance d- 5 - - 5 -pf table 6. specific characteristics ?continued v dda1v2 = 1.2 v; v ddd1v2 = 1.2 v; typical values measured at t amb = +25 ? c; r l = 50 ? ; i o(fs) = 20 ma; maximum sample rate used; no inverse (sinus x) / x; no output correction; output level = 1 v (p-p); unless otherwise specified. symbol parameter conditions test dac1658q: high common-mode DAC1653Q: low common-mode unit min typ max min typ max
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 15 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 10. dynamic characteristics table 7. dynamic characteristics dac165xq1g5 v dda1v2 = 1.2 v; v ddd1v2 = 1.2 v; typical values measured at t amb = +25 ? c; rl = 50 ? ; i o(fs) = 20 ma; maximum sample rate used; no auxiliary dac; no inverse (sinus x) / x; no output correction; output level = 1 v (p-p); unless otherwise specified. symbol parameter conditions test [1] dac1658q: high common-mode DAC1653Q: low common-mode unit min typ max min typ max sfdr spurious-free dynamic range f data = 737.28 mhz; f s = 1474.56 msps; b = f s / 2 v dda = 3.3 v; f o = 20 mhz at ? 1 dbfs i - 85 - - 85 - dbc at ? 7 dbfs i - - - - dbc at ? 14 dbfs i - - - - dbc v dda = 3.3 v; f o = 150 mhz at ? 1 dbfs i - 83 - - 81 - dbc at ? 7 dbfs i - - - - dbc at ? 14 dbfs i - - - - dbc v dda = 2.5 v; f o = 20 mhz at ? 1 dbfs i n.a. - 83 - dbc at ? 7 dbfs i n.a. - - dbc at ? 14 dbfs i n.a - - dbc v dda = 2.5 v; f o = 150 mhz at ? 1 dbfs i n.a. - 81 - dbc at ? 7 dbfs i n.a. - - dbc at ? 14 dbfs i n.a. - - dbc sfdr (rbw) spurious-free dynamic range restricted bandwidth v dda = 3.3 v; f o = 230 mhz b = 300 mhz at ? 1 dbfs i - - - - dbc imd3 third-order intermodulation distortion v dda = 3.3 v; f o1 = 20 mhz; f o2 = 21 mhz; ? 7 dbfs per tone i - 86 - - 86 - dbc v dda = 3.3 v; f o1 = 230 mhz; fo2 = 231 mhz; ? 7 dbfs per tone i - 84 - - 82 - dbc
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 16 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps [1] d = guaranteed by design; c = guaranteed by characterization; i = 100 % industrially tested. acpr adjacent channel power ratio f o = 40 mhz 1 wcdma carrier; b = 5 mhz c - 82 - - 82 - dbc 4 wcdma carriers; b = 20 mhz c - 75 - - 75 - dbc alt-acpr alternate channel power ratio f o = 40 mhz 1 wcdma carrier; b = 5 mhz c - - - - dbc 4 wcdma carriers; b = 20 mhz c - - - - dbc nsd noise spectral density f o = 20 mhz at ? 1 dbfs c - -164 - - ? 162 - dbm/hz table 7. dynamic characteristics dac165xq1g5 ?continued v dda1v2 = 1.2 v; v ddd1v2 = 1.2 v; typical values measured at t amb = +25 ? c; rl = 50 ? ; i o(fs) = 20 ma; maximum sample rate used; no auxiliary dac; no inverse (sinus x) / x; no output correction; output level = 1 v (p-p); unless otherwise specified. symbol parameter conditions test [1] dac1658q: high common-mode DAC1653Q: low common-mode unit min typ max min typ max
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 17 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps table 8. dynamic characteristics dac165xq1g25 v dda1v2 = 1.2 v; v ddd1v2 = 1.2 v; typical values measured at t amb = +25 ? c; rl = 50 ? ; i o(fs) = 20 ma; maximum sample rate used; no auxiliary dac; no inverse (sinus x) / x; no output correction; output level = 1 v (p-p); unless otherwise specified. symbol parameter conditions test [1] high common-mode low common-mode unit min typ max min typ max sfdr spurious-free dynamic range f data = 614.4 mhz; f s = 1228.8 msps; b = f s / 2 v dda = 3.3 v; f o = 20 mhz at ? 1 dbfs i - 85 - - 85 - dbc at ? 7 dbfs i - - - - dbc at ? 14 dbfs i - - - - dbc v dda = 3.3 v; f o = 150 mhz at ? 1 dbfs i - 83 - - 81 - dbc at ? 7 dbfs i - - - - dbc at ? 14 dbfs i - - - - dbc v dda = 2.5 v; f o = 20 mhz at ? 1 dbfs i n.a. - 83 - dbc at ? 7 dbfs i n.a. - - dbc at ? 14 dbfs i n.a - - dbc v dda = 2.5 v; f o = 150 mhz at ? 1 dbfs i n.a. - 81 - dbc at ? 7 dbfs i n.a. - - dbc at ? 14 dbfs i n.a. - - dbc sfdr (rbw) spurious-free dynamic range restricted bandwidth v dda = 3.3 v; f o = 230 mhz b = 300 mhz at ? 1 dbfs i - - - - dbc imd3 third-order intermodulation distortion v dda = 3.3 v; f o1 = 20 mhz; f o2 = 21 mhz; ? 7 dbfs per tone i - 86 - - 86 - dbc v dda = 3.3 v; f o1 = 230 mhz; fo2 = 231 mhz; ? 7 dbfs per tone i - 84 - - 82 - dbc acpr adjacent channel power ratio f o = 40 mhz 1 wcdma carrier; b = 5 mhz c - 82 - - 82 - dbc 4 wcdma carriers; b = 20 mhz c - 75 - - 75 - dbc
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 18 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps [1] d = guaranteed by design; c = guaranteed by characterization; i = 100 % industrially tested. alt-acpr alternate channel power ratio f o = 40 mhz 1 wcdma carrier; b = 5 mhz c - - - - dbc 4 wcdma carriers; b = 20 mhz c - - - - dbc nsd noise spectral density f o = 20 mhz at ? 1 dbfs c - -164 - - ? 162 - dbm/hz table 8. dynamic characteristics dac165xq1g25 ?continued v dda1v2 = 1.2 v; v ddd1v2 = 1.2 v; typical values measured at t amb = +25 ? c; rl = 50 ? ; i o(fs) = 20 ma; maximum sample rate used; no auxiliary dac; no inverse (sinus x) / x; no output correction; output level = 1 v (p-p); unless otherwise specified. symbol parameter conditions test [1] high common-mode low common-mode unit min typ max min typ max
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 19 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps table 9. dynamic characteristics dac16qxd1g0 v dda1v2 = 1.2 v; v ddd1v2 = 1.2 v; typical values measured at t amb = +25 ? c; rl = 50 ? ; i o(fs) = 20 ma; maximum sample rate used; no auxiliary dac; no inverse (sinus x) / x; no output correction; output level = 1 v (p-p); unless otherwise specified. symbol parameter conditions test [1] high common-mode low common-mode unit min typ max min typ max sfdr spurious-free dynamic range f data = 491.52 mhz; f s = 983.04 msps; b = f s / 2 v dda = 3.3 v; f o = 20 mhz at ? 1 dbfs i - 85 - - 85 - dbc at ? 7 dbfs i - - - - dbc at ? 14 dbfs i - - - - dbc v dda = 3.3 v; f o = 150 mhz at ? 1 dbfs i - 83 - - 81 - dbc at ? 7 dbfs i - - - - dbc at ? 14 dbfs i - - - - dbc v dda = 2.5 v; f o = 20 mhz at ? 1 dbfs i n.a. - 83 - dbc at ? 7 dbfs i n.a. - - dbc at ? 14 dbfs i n.a - - dbc v dda = 2.5 v; f o = 150 mhz at ? 1 dbfs i n.a. - 81 - dbc at ? 7 dbfs i n.a. - - dbc at ? 14 dbfs i n.a. - - dbc sfdr (rbw) spurious-free dynamic range restricted bandwidth v dda = 3.3 v; f o = 230 mhz b = 300 mhz at ? 1 dbfs i - - - - dbc imd3 third-order intermodulation distortion v dda = 3.3 v; f o1 = 20 mhz; f o2 = 21 mhz; ? 7 dbfs per tone i - 86 - - 86 - dbc v dda = 3.3 v; f o1 = 230 mhz; fo2 = 231 mhz; ? 7 dbfs per tone i - 84 - - 82 - dbc acpr adjacent channel power ratio f o = 40 mhz 1 wcdma carrier; b = 5 mhz c - 82 - - 82 - dbc 4 wcdma carriers; b = 20 mhz c - 75 - - 75 - dbc
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 20 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps [1] d = guaranteed by design; c = guaranteed by characterization; i = 100 % industrially tested. alt-acpr alternate channel power ratio f o = 40 mhz 1 wcdma carrier; b = 5 mhz c - - - - dbc 4 wcdma carriers; b = 20 mhz c - - - - dbc nsd noise spectral density f o = 20 mhz at ? 1 dbfs c - -164 - - ? 162 - dbm/hz table 9. dynamic characteristics dac16qxd1g0 ?continued v dda1v2 = 1.2 v; v ddd1v2 = 1.2 v; typical values measured at t amb = +25 ? c; rl = 50 ? ; i o(fs) = 20 ma; maximum sample rate used; no auxiliary dac; no inverse (sinus x) / x; no output correction; output level = 1 v (p-p); unless otherwise specified. symbol parameter conditions test [1] high common-mode low common-mode unit min typ max min typ max
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 21 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps fig 3. sfdr(dbc) over nyquist depending of fout (mhz) fig 4. sfdr(dbc) ecxluding hd2 and hd3 over nyquist depending of fout (mhz)
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 22 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps fig 5. acpr(dbc) lte 1 carrier 5 mhz depending of fout (mhz)
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 23 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 11. application information 11.1 general description the dac165xq is a quad 16-bit dac operating up to 1.50 gsps. a maximum input data rate up to 750 msps is supported to enable more capability for wideband and multicarrier systems. the incorporated quadrature modulators and 40-bit numerically controlled oscillators (ncos) simplify the frequency selection of the system. this is also possible because of the ? 2, ? 4 or ? 8 interpolation filters which remove undesired images. the dac165xq embeds four dac channels (a, b, c and d) that can be configured as a single quad dac (a/b/c/d) or two dual dacs (a/b and c/d). the two ncos are linked to the a/b and the c/d dual dacs, respectively. regarding the quad/dual mode used, the eight jesd204b lanes are configured as one single link configuration jesd204 link (one sync signal for a specified number of lanes), or dual link configuration jesd204b links (two sync signals associated with a specified number of lanes). the dac165xq supports the following jesd204b key features: ? 10-bit/8-bit decoding ? code group synchronization ? initial-lane alignment (ila) ? 1 + x 14 + x 15 scrambling polynomial ? character replacement ? tx/rx synchronization management via synchronization signals ? multiple converter device alignment-multiple lanes (mcda-ml) device ? number l of serial lanes: 1, 2, 4, 8 (see lmf configuration table) ? number m of data converters: 1, 2 or 4 (see lmf configuration table) ? number f of octets per frame: 1, 2, 4, 6, 8 (see lmf configuration table) ? number s of samples per frame: 1, 2 (see lmf configuration table) ? embedded test pattern (prbs7; prbs15; prbs23, prbs31, jtspat, stltp) the dac165xq can be interfaced with any logic device that features high-speed serializer/deserializer (serdes) functionality. this macro is now widely available in field-programmable gate array (fpga) of different vendors. standalone serdes ics can also be used. the device includes polarity swapping for each of the lanes and additionally offers lane swapping to enhance the intrinsic board layout simplification of the jesd204b standard. each physical lane can be configured logically as any lane number. this device is mcda-ml compliant, offering inter-lane alignment between several devices. an idt proprietary mechanism in combination with the jesd204b subclass i clause enables maintenance of sample alignment between devices up to the final analog output stage. output samples are automatically aligned to the sysref signal generated by a dedicated ic or by the fpga itself. a system with several dac165xqs can produce data with a guaranteed alignment of 1 dac output clock period. the dac165xq incorporates two differential sysref ports (located on opposite sides of the ic). these
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 24 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps can be programmed to act as an input or an output regarding the mode expected for the system (normal mode, daisy chain mode). the device also enables independent link reinitialization. the dac165xq generates four complementary current outputs on pins iouta_p/iouta_n and ioutb_p/ioutb_n, ioutc_p/ioutc_n, and ioutd_p/ioutd_n corresponding to channel 'a', ?b?, ?c?, and 'd', respectively, providing a nominal full-scale output current of 20 ma. an internal reference is available for the reference current which is externally adjustable using pin vires. the dac165xq requires configuration before operating. it features an spi slave interface to access the internal registers. some of these registers also provide information about the jesd204b interface status. optionally, an interrupt capability can be programmed using those registers to ensure ease of use of the device. because of the jesd204b standardization, the dac165xq does not require any adjustment from the transmit logic device (tld) to capture the input data streams. some autolock features can be monitored using the spi registers. the dac165xq supports the following lmf configuration as described in the jesd204b standard. [1] s is the number of samples per frame. [2] hd is the high-density bit as described in the jesd204b specification. a new idt auto-mute feature enables switching off of the rf output signal as a result of various internal events occurring. a signal level detector allows auto-muting of the dac outputs if they exceed the detection limit. the dac165xq requires supplies of 2.5 v or 3.3 v and 1.2 v. the 1.2 v supply has separate digital and analog power supply pins . table 10. lmf configuration if dac165xq configures in dual jeds204b links link configuration l-m-f s [1] hd [2] dual link 1-2-4 1 0 dual link 2-2-2 1 0 dual link 4-2-2 2 0 dual link 4-2-1 1 1 single link 2-4-4 1 0 single link 4-2-2 1 0 single link 8-4-2 2 0 single link 8-4-1 1 1
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 25 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps fig 6. independent/dual link configuration lmf=421 lane ab0 lane ab1 lane ab2 lane ab3 lmf=422 lmf=222 lmf=124 q ab0 [7-0] q ab1 [7-0] q ab2 [7-0] i ab0 [7-0] i ab 1 [7-0] i ab2 [7-0] q ab0 [15-8] q ab1 [15-8] q ab2 [15-8] i ab0 [15-8] i ab1 [15-8] i ab2 [15-8] q ab1 [15-8] q ab1 [7-0] q a b 3 [15-8] i ab1 [15-8] i ab1 [7-0] i ab3 [15-8] q ab0 [15-8] q ab0 [7-0] q ab2 [15-8] i ab0 [15-8] i ab0 [7-0] i ab2 [15-8] q ab0 [15-8] q ab0 [7-0] q ab1 [15-8] q a b 1 [7-0] i ab0 [15-8] i ab0 [7-0] i ab1 [15-8] i ab1 [17-0] i ab0 [15-8] i ab0 [7-0] q ab0 [15-8] qab 0 [7-0] lane cd0 lane cd1 lane cd2 lane cd3 q cd0 [7-0] q cd1 [7-0] q cd 2 [7-0] i cd0 [7-0] i cd1 [7-0] i cd2 [7-0] q cd0 [15-8] q cd1 [15-8] q cd2 [15-8] i cd0 [15-8] i cd1 [15-8] i cd2 [15-8] q cd1 [15-8] q cd1 [7-0] q c d 3 [15-8] i cd1 [15-8] i cd1 [7-0] i cd3 [15-8] q cd0 [15-8] q cd0 [7-0] q cd2 [15-8] i cd0 [15-8] i cd0 [7-0] i cd2 [15-8] q cd0 [15-8] q cd0 [7-0] q cd1 [15-8] q cd1 [7-0] i cd0 [15-8] i cd0 [7-0] i cd1 [15-8] i cd1 [17-0] i cd0 [15-8] i cd0 [7-0] q cd0 [15-8] q c d 0 [7-0] link ab link cd
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 26 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 11.2 device operation the dac165xq provides a lot of flexibility in its way of working through its spi registers. the spi registers are divided in blocks of registers. each block is associated with some global functions which are described below. fig 7. spi register blocks partition: dac a/b power on/off sleep clock distribution clock generation direct mode/ divide by 2 mode daca dacb vin_ab_p3 vin_ab_n3 syncb_ab_p syncb_ab_n vin_ab_p2 vin_ab_n2 vin_ab_p1 vin_ab_n1 vin_ab_p0 l0 eq l1 l2 l3 vin_ab_n0 auto cal equalizer control block 0040h: main controls monitoring control mds managment sysref east sysref west interrupts block 0120h/0140h: jesd204 read configuration did, bid, adj_cnt, adj_dir, ph_adj, scr, l, f, k, m, n, n, sbclss_vs, s, hd, cf, jesd_vs, res1, res2, fchk block 0160h: rx phy block 00c0h: rx dlp block 0060h: interface dac dsp block 0020h: dual dac core block 0180h: rx phy monitoring auto equalizer cdr termination calibration lanes lock ila monitoring error detection simple ber flags counter block 00e0h: rx dlp monitoring block 00a0h: mutiples devices synchronization/interrupts eq eq eq sync mgmt lane polarity 8b/10b scramblers ila swap lanes sample assembly input data format interpolation filters ~x1, x2, x4, x8 single side band modulation (nco) i/q dc level control phase correction level detector gain gain automute (block x0800) offset offset signal level detection
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 27 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 11.2.1 spi configuration block this block of registers specifies how the spi controller and the identification of the chip work. 11.2.1.1 protocol description the dac165xq serial interface is a synchronous serial communication port allowing easy interfacing with many industry microprocessors. it provides access to the registers that define the operating modes of the chip in both write mode and read mode. the reference voltage of the interface is v ddd(io) . depending on the power supply level of the spi master device, it can be set to either 1.2 v or 1.8 v. this interface can be configured as a 3-wire type (sdio as bidirectional pin) or a 4-wire type (sdio and sdo as unidirectional pins, input and output ports, respectively). in both configurations, sclk acts as the serial clock and scs_n acts as the serial chip select. the dac165xq spi-interface is a slave-device. multiple slave-devices can be attached to the same master interface as long as each device has its own serial chip select signal (scs_n). fig 8. spi register blocks partition: dac c/d power on/off sleep clock distribution clock generation direct mode/ divide by 2 mode dacc dacd vin_cd_p3 vin_cd_n3 syncb_cd_p syncb_cd_n vin_cd_p2 vin_cd_n2 vin_cd_p1 vin_cd_n1 vin_cd_p0 l0 eq l1 l2 l3 vin_cd_n0 mds managment sysref east sysref west interrupts block 0320h/0340h: jesd204 read configuration did, bid, adj_cnt, adj_dir, ph_adj, scr, l, f, k, m, n, n, sbclss_vs, s, hd, cf, jesd_vs, res1, res2, fchk block 0360h: rx phy block 02c0h: rx dlp block 0260h: interface dac dsp block 0220h: dual dac core block 0380h: rx phy monitoring auto equalizer cdr termination calibration lanes lock ila monitoring error detection simple ber flags counter block 02e0h: rx dlp monitoring block 02a0h: mutiples devices synchronization/interrupts eq eq eq sync mgmt lane polarity 8b/10b scramblers ila swap lanes sample assembly input data format interpolation filters ~x1, x2, x4, x8 single side band modulation (nco) i/q dc level control phase correction level detector gain gain automute (block x0280) offset offset signal level detection auto cal equalizer control block 0240h: main controls monitoring control
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 28 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps a[14:0] indicates which register is being addressed. if a multiple transfer occurs, this address points to the first register to be accessed. 11.2.1.2 spi controller configuration the 3-wire or 4-wire mode is set by bit spi_4w of register spi_cfg_a . the default mode is 3-wire mode. a software spi reset can be called via bit spi_rst of register spi_cfg_a . this reset reinitializes all spi registers, except register spi_cfg_a and spi_cfg_b, to their default settings. reset the device to its default value at start-up time to avoid any uncontrolled states, even if the dac165xq uses the power-on reset (por) module. only a hardware reset on pin reset_n can reset to their default values. the spi streaming mode is enabled by default. in this mode, the read or write process carries on as long as the scs_n signal is low. the streaming mode requires a first address 'n' to be set at the beginning of the spi sequence. the following data are associated from this address in an ascending (auto-increment) or descending (auto-decrement) mode. this ascending/descending mode is specified by bit spi_asc of register spi_config_a . figure 10 and figure 1 1 show the read back of 2 bytes data in a 3-wire mode for the ascendant and descendant mode. r/w indicates the mode access. the reset_n signal is not linked to the spi interface but enable the reset of the registers to the default values. fig 9. spi protocol reset_n scs_n sclk sdio sdo (optional) r/w a14 a13 a4 a3 a2 a1 a0 d7 d6 d5 a12 a11 a10 a9 a8 a7 a6 a5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 table 11. read mode or write mode access description r/w description 0 write mode operation 1 read mode operation fig 10. consecutive 2-byte data readback under descending address address n register n value register n - 1 value scs_n sclk sdio r/w a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 29 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps the streaming mode can be disabled by setting bit spi_sngl of register spi_config_b . in this single-byte mode, only 1 byte of data can be written or read, whatever the state of the scs_n signal. 11.2.1.3 double buffering and transfer mode some register functions (like the nco frequency value) are split over multiple registers. if this is the case, the first address consists of the lsb byte and the highest address in the msb byte. when programming these registers sequentially, some unexpected behavior can occur at the dac output. it is preferable to program this set of registers simultaneously. a double buffering feature is available on some registers allowing sequential programming of the first buffers and transfering the values to the final register simultaneously. the transfer request is done by setting the transfer_bit bit of register spi_config_c register . the device clears this bit (autoclear) indicating to the spi master device that the transfer is complete. the spi_rback_buff bit of register spi_config_b allows the reading back of the first stage of buffers (in case the register is double buffered) the following registers are double buffered: fig 11. consecutive 2-byte data readback under ascending address address n register n value register n + 1 value scs_n sclk sdio r/w a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 table 12. double buffered registers address register 0062h/0262h/046ah nco_ph_offset_xy_lsb 0063h/0263h/0463h nco_ph_offset_xy_msb 0064h/0264h/0464h nco_freq_xy_b0 0065h/0265h/0465h nco_freq_xy_b1 0066h/0266h/0466h nco_freq_xy_b2 0067h/0267h/0467h nco_freq_xy_b3 0068h/0268h/0468h nco_freq_xy_b4 0069h/0269h/0469h ph_corr_xy_ctrl_0 006ah/026ah/046ah ph_corr_xy_ctrl_1 006bh/026bh/046bh dac_x_dgain_lsb 006ch/026ch/046ch dac_x_dgain_msb 006dh/026dh/046dh dac_y_dgain_lsb 006eh/026eh/046eh dac_y_dgain_msb 006fh/026fh/046fh dac_out_ctrl_xy 0070h/0270h/0470h dac_lvl_det_xy 0071h/0271h/0471h dac_x_offset_lsb 0072h/0272h/0472h dac_x_offset_msb
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 30 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 11.2.1.4 device description registers chip_type, chip_id_0, chip_id_1 and chip_vs represent the id card of the device. registers vend_id_lsb and vend_id_msb represent the idt manufacturer identifier. 11.2.1.5 spi timing description the spi interface can operate at a frequency of up to 25 mhz. figure 12 shows the spi timing. the spi timing characteristics are given in t able 13 . 0073h/0273h/0473h dac_y_offset_lsb 0074h/0274h/0474h dac_y_offset_msb 0075h/0275h/0475h iq_lvl_ctrl 0076h/0276h/0476h i_dc_lvl_xy_lsb 0077h/0277h/0477h i_dc_lvl_xy_msb 0078h/0278h/0478h q_dc_lvl_xy_lsb 0079h/0279h/0479h q_dc_lvl_xy_msb table 12. double buffered registers ?continued address register fig 12. spi timing diagram 50 % t w(reset_n) t su(scs_n) t su(sdio) t h(sdio) t h(scs_n ) t w(sclk) 50 % r eset_n scs_n sclk sdio 50 % 50 %
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 31 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps [1] the reset_n signal is not linked to the spi interface, but enables the reset of the registers to the default values. 11.2.2 main device configuration the registers of block main are used for the main configuration of the dac165xq. at start-up, the two clocks wclk and dclk are forced to reset states to avoid that the dac outputs any dummy signal through bits force_rst_dclk and force_rst_wclk of the main_ctrl register . the device configuration has to be done before releasing these two clocks. here are some guidelines to ensure correct spi programming. as dclk and wclk are kept to reset the programming sequence of the registers is not important: other spi configurations can be added using these basic settings. table 13. spi timing characteristics symbol parameter min typ max unit f sclk sclk frequency - - 25 mhz t w(sclk) sclk pulse width 30 - - ns t su(scs_n) scs_n set-up time 20 - - ns t h(scs_n) scs_n hold time 20 - - ns t su(sdio) sdio set-up time 10 - - ns t h(sdio) sdio hold time 5 - - ns t w(reset_n) reset_n pulse width [1] 30 - - ns fig 13. main controls io_sel_2 io0 io_sel_0 io0 io_sel_1 io_en 0 io_en 1 interface dac dsp mon_dclk block 0060h mon_dclk_stop cdi cdi_mod ^2 mode ^4 mode ^8 mode dlp sr_cdi rx ip auto_cal_eqz auto_cal_rt q_dc_lvl_xy q_lvl_ctrl_xy dac b/d i_dc_lvl_xy i_lvl_ctrl_xy dac a/c vin_ab_p3/vin_cd_p3 vin_ab_n3/vin_cd_n3 dclk (see block 0020h) wclk (see block 0020h) force_rst_wclk rst_ext_wclk_time force_rst_dclk rst_ext_dclk_time start-up management vin_ab_p2/vin_cd_p2 vin_ab_n2/vin_cd_n2 vin_ab_p1/vin_cd_p1 vin_ab_n1/vin_cd_n1 vin_ab_p0/vin_cd_p0 poff_rx man_pon_ctrl l0 l1 l2 l3 vin_ab_n0/vin_cd_n0 eq eq eq eq block 0040h: main controls
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 32 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 11.2.3 interface dac dsp block this module is the interface between the data processing in the high-speed serial receiver and the dual dac core. the controls of the digital signal processing (dsp) of the dac are specified to set up the interpolation filter, and enable or disable the various gains and offsets of the data digital path. the data signals have already been processed by the digital lane processing . they are provided to this module through the clock domain interface . this module is clocked by the digital clock dclk. 11.2.3.1 input data format after decoding in the high-speed serial receiver, the data representation can be specified as binary offset coding or as two's complement coding using register coding_xy_iq . 11.2.3.2 finite impulse response (fir) filters the dac165xq provides three interpolation filters described by their coefficients in t able 15 . the three interpolation fir filters have a stop band attenuation of at least 80 dbc and a pass band ripple of less than 0.0005 db. the interpolation ratio can be set through register tx_cfg_xy . the 'no interpolation' or '~ ? 1' (quasi ? 1) mode is in fact a degenerated ? 2 interpolation mode where the samples are repeated twice. block 0060h = dac a/b block 0260h = dac c/d block 0460h = all dacs fig 14. interface dac dsp overview block 0060h/0260h/0460h: interface dac dsp level detector offset x dac_x_offset dac_lvl_det_xy inverse sin x / x phase correction interpolation filters input data format coding: binary offset twos complement interpolation: ~1 (sample repetition) x2 x4 x8 inv_sinc_sel_xy lvl_det_en_xy minus_3db_xy offset y dac_y_offset dgain x dac_x_dgain ph_corr_xy dgain y dac_y_dgain auto mute (see specific diagram; block 0080h) dac_x_dgain_en dac_y_dgain_en ph_corr_en_xy nco_on_xy single side band modulation (nco) nco_lp_sel_xy nco_freq_xy nco_ph_xy modulation: pos.up.sideband pos.low.sideband neg.up.sideband neg.low.sideband + + x2 table 14. interpolation symbol access value description interpolation[1:0] r/w interpolation 00 no interpolation/~ ? 1 interpolation 01 ? 2 interpolation 10 ? 4 interpolation 11 ? 8 interpolation
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 33 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps remark: the interpolation setting must be coupled with the dclk and wclk clock configurations and with cdi mode . fig 15. first stage half-band filter response (used in ? 2, ? 4, and ? 8 interpolation) fig 16. second stage half-band filter response (used in ? 2, ? 4, and ? 8 interpolation) nf (fs) 0 0.5 0.4 0.2 0.3 0.1 magnitude (db) 0 -100 -20 -40 -80 -60 nf (fs) 0 0.5 0.4 0.2 0.3 0.1 magnitude (db) 0 -100 -20 -40 -80 -60
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 34 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps fig 17. third stage half-band filter response (used in ? 2, ? 4, and ? 8 interpolation) table 15: interpolation filter coefficients first interpolation filter second interpolation filter third interpolation filter lower upper value lower upper value lower upper value - h(27) +65536 h(11) - +32768 h(7) - +1024 h(26) h(28) +41501 h(10) h(12) +20272 h(6) h(8) +615 h(25) h(29) 0 h(9) h(13) 0 h(5) h(9) 0 h(24) h(30) ? 13258 h(8) h(14) ? 5358 h(4) h(10) ? 127 h(23) h(31) 0 h(7) h(15) 0 h(3) h(11) 0 h(22) h(32) +7302 h(6) h(16) +1986 h(2) h(12) +27 h(21) h(33) 0 h(5) h(17) 0 h(1) h(13) 0 h(20) h(34) ? 4580 h(4) h(18) ? 654 h(0) h(14) ? 3 h(19) h(35) 0 h(3) h(19) 0 - - - h(18) h(36) +2987 h(2) h(20) +159 - - - h(17) h(37) 0 h(1) h(21) 0 - - - h(16) h(38) ? 1951 h(0) h(22) ? 21--- h(15) h(39) 0 - - ---- h(14) h(40) +1250 - - ---- h(13) h(41) 0 - - ---- h(12) h(42) -773 - - ---- h(11) h(43) 0 - - ---- h(10) h(44) +456 - - ---- h(9) h(45) 0 - - ---- h(8) h(46) ? 252------ h(7) h(47) 0 - - ---- h(6) h(48) +128 - - ---- h(5) h(49) 0 - - ---- h(4) h(50) ? 58------ nf (fs) 0 0.5 0.4 0.2 0.3 0.1 magnitude (db) 0 -100 -20 -40 -80 -60
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 35 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps the dependency of the fir1 output y(m) on its inputs x(m) is defined by equation 1 : (1) the dependency of the fir2 output y(m) on its inputs x(m) is defined by equation 2 : (2) the dependency of the fir3 output y(m) on its inputs x(m) is defined by equation 3 : (3) 11.2.3.3 single sideband modulator (ssbm) the single sideband modulator is a quadrature modulator that enables the mixing of the i_xy data and q_xy data with the sine and cosine signals generated by the nco to generate path x and y as described in figure 18 . h(3) h(51) 0 - - ---- h(2) h(52) +22 - - ---- h(1) h(53) 0 - - ---- h(0) h(54) ? 6------ table 15: interpolation filter coefficients ?continued first interpolation filter second interpolation filter third interpolation filter lower upper value lower upper value lower upper value y m ?? 1 h27 ?? --------------- - hn ?? : xm n ? ?? ?? n0 = n54 = ? ? = y m ?? 1 h11 ?? --------------- - hn ?? : xm n ? ?? ?? n0 = n22 = ? ? = y m ?? 1 h7 ?? ------------ - hn ?? : xm n ? ?? ?? n0 = n14 = ? ? = fig 18. single sideband modulator principle +/ ? cos x y i_xy sin +/ ? sin q _xy cos +/ ?
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 36 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps t able 16 shows the various possibilities set by register modulation . table 16. complex modulator operation mode modulation[2:0] mode path x path y 000 bypass 001 positive upper sideband 010 positive lower sideband 011 negative upper sideband 100 negative lower sideband others not defined - - i _ xy t ?? q _ xy t ?? i _ xy t ?? ? nco _ xy t ? ?? cos q _ xy t ?? ? nco _ xy t ? ? ? sin ? ? ? i _ xy t ?? ? nco _ xy t ? ?? sin q _ xy t ?? ? nco _ xy t ? ? ? cos ? + ? i _ xy t ?? ? nco _ xy t ? ?? cos q _ xy t ?? ? nco _ xy t ? ? ? sin ? + ? i _ xy t ?? ? nco _ xy t ? ?? sin q _ xy t ?? ? nco _ xy t ? ? ? cos ? ? ? i _ xy t ?? ? nco _ xy t ? ?? cos q _ xy t ?? ? nco _ xy t ? ? ? sin ? ? ? i _ xy t ?? ? z nco _ xy t ? ?? sin q _ xy t ?? ? nco _ xy t ? ? ? cos ? ? ? i _ xy t ?? ? nco _ xy t ? ?? cos q _ xy t ?? ? nco _ xy t ? ? ? sin ? + ? i _ xy t ?? ? z nco _ xy t ? ?? sin q _ xy t ?? ? nco _ xy t ? ? ? cos ? + ?
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 37 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps the effect of the modulation parameter is better viewed after mixing the x and y signal with a lo frequency through an iq modulator. 11.2.3.4 40-bit nco the ssbm used the complex signals coming from the nco (numeric complex oscillator) to mix the i and q signals. the 5 registers nco_freq_xy_b0 to nco_freq_xy_b4 over 40 bits can set the frequency. the frequency is calculated with equation 4 : (4) where: ? m is the value set in the bits nco_freq_xy[39:0] of the nco frequency registers . ? f s is the final dac output clock sampling frequency the registers nco_ph_offset_xy_lsb and nco_ph_offset_xy_msb over 16 bits from 0 ? to 360 ? can set the phase of the nco. the default settings represent an nco frequency of 96 mhz when using a dac clock of 640 msps. for other dac clock frequencies, use equation 4 to define the associated nco frequency. 11.2.3.5 nco low power when using nco low power (bit nco_lp_sel_xy), the five most significant bits of register nco_freq_xy_b4 (bits nco_freq_xy[39:32]; bits [31:0] are masked by zero) can set the frequency. the frequency is calculated with equation 5 : (5) where: ? m is the value set in the bits nco_freq_xy[39:0] of the nco frequency registers . ? f s is the dac clock sampling frequency 11.2.3.6 inverse sinx / x a selectable fir filter is incorporated to compensate the sinx / x effect caused by the roll-off effect of the dac. the coefficients are represented in t able 17 . this feature is controlled by register inv_sinc_sel_xy fig 19. complex modulation after lo mixing 0 lo-nco negative positive lower upper lower upper lo+nco lo frequency f nco mf s ? 2 40 --------------- -- - = f nco mf s ? 2 40 --------------- -- - =
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 38 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps remark: the transfer function of this features adds some gain to the signals and some saturation can occur with a level of distortion in the output spectrum as result. update the digital gain accordingly to avoid this saturation. 11.2.3.7 minus 3db during normal operation, a full-scale pattern is also full-scale at the dac output. when the i data and the q data approach full-scale simultaneously, saturation can occur. the minus 3db function (bit minus_3db_xy of register dac_out_ctrl_xy) can be used to reduce the 3 db gain in the modulator. it retains a full-scale range at the dac output without added interferers. 11.2.3.8 phase correction the iq modulator which follows the dacs can have a phase imbalance resulting in undesired sidebands. by adjusting the phase between the i and q channels, the unwanted sideband can be reduced. without compensation the i and q channels have a phase difference of ? / 2 (90). the registers ph_corr_xy_ctrl_0 and ph_corr_xy_ctrl_1 ensure a phase variation from 75.7 ? to 104.3 ? by steps 0.0035 ? . the two registers define a signed value that ranges from ? 4096 to +4095. the equation: ph_corr[12:0] / 16384 gives the resulting phase compensation (in radians). the phase correction can be enabled by register ph_corr_en_xy . 11.2.3.9 digital gain the full-scale output current for each dac is the sum of the two complementary current outputs: ? ? ? ? the iq-modulator can have an amplitude imbalance which results in undesired sidebands. the unwanted sideband can be reduced by adjusting the amplitude of signals a and b. the two gains are purely digital and could be enabled by registers dac_x_dgain_en and dac_y_dgain_en . the output current of dac x depends on the digital input data and the gain factor defined by bits dac_x_dgain[11:0] of register dac_x_dgain_msb and register dac_x_dgain_lsb . table 17. inversion filter coefficients inversion filter lower upper value h(1) h(9) +1 h(2) h(8) ? 4 h(3) h(7) +13 h(4) h(6) ? 51 h(5) - +610 i oa fs ?? i iouta _ p i iouta _ n + = i ob fs ?? i ioutb _ p i ioutb _ n + = i ob fs ?? i ioutc _ p i ioutc _ n + = i ob fs ?? i ioutd _ p i ioutd _ n + =
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 39 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps (6) (7) (8) (9) the output current of dac b depends on the digital input data and the gain factor defined by bits dac_y_dgain[11:0] of register dac_y_dgain_msb and dac_y_dgain_lsb . (10) (11) (12) (13) t able 18 shows the output current as a function of the input data, when i oa(fs) = i ob(fs) = 20 ma. 11.2.3.10 auto-mute the dac165xq provides a new auto-mute feature allowing muting the dac analog output if a conditional event occurs. the auto-mute feature is based on a state machine as described in figure 21 and on the control of the digital gains. table 18. dac transfer function data i15 to i0/q15 to q0 (binary coding) i15 to i0/q15 to q0 (two?s complement coding iouta_p/ ioutb_p iouta_n/ ioutb_n 0 0000 0000 0000 0000 1000 0000 0000 0000 0 ma 20 ma ... ... ... ... .... 32768 1000 0000 0000 0000 0000 0000 0000 0000 10 ma 10 ma ... ... ... ... ... 65535 1111 1111 1111 1111 0111 1111 1111 1111 20 ma 0 ma i iouta _ p i oa fs ?? dac _ x _ dgain ?? 4096 -------------------------------------------------- data 65535 --------------- - ? ? ? ? ? ? = i iouta _ n i oa fs ?? 1 dac _ x _ dgain ?? 4096 -------------------------------------------------- data 65535 --------------- - ?? ?? ? ? ? ? ? ? ? = i ioutc _ p i oa fs ?? dac _ x _ dgain ?? 4096 -------------------------------------------------- data 65535 --------------- - ? ? ? ? ? ? = i ioutc _ n i oa fs ?? 1 dac _ x _ dgain ?? 4096 -------------------------------------------------- data 65535 --------------- - ?? ?? ? ? ? ? ? ? ? = i ioutb _ p i ob fs ?? dac _ y _ dgain ?? 4096 ------------------------------------------------- data 65535 --------------- - ? ? ? ? ? ? = i ioutb _ n i ob fs ?? 1 dac _ y _ dgain ?? 4096 ------------------------------------------------- data 65535 --------------- - ?? ?? ? ? ? ? ? ? ? = i ioutd _ p i ob fs ?? dac _ y _ dgain ?? 4096 ------------------------------------------------- data 65535 --------------- - ? ? ? ? ? ? = i ioutd _ n i ob fs ?? 1 dac _ y _ dgain ?? 4096 ------------------------------------------------- data 65535 --------------- - ?? ?? ? ? ? ? ? ? ? =
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 40 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps in normal operating mode, the state machine is in idle state. the digital gains are specified by the user. various mute events can be detected in the dac. these trigger the mute state. once the mute state is entered, the dac automatically sets the digital gains to zero using several mute actions. the mute actions soft mute and hold mute drop to zero gradually. the mute action hard mute drop to zero instantly (see figure 22 ). when the digital gains have been set to zero, the state machine enters the wait state. in this state, the gains are kept at zero. the state machine stays in this mode until the end of the wait period and the mute event is not deasserted. when the mute event is cleared and the wait period elapsed, the state machine enters the demute state. in this state, the digital gains are set again to the initial values. this is done relatively to the mute rate setting. if during this state, a new mute event is triggered, the state machine enters the mute state again. the gain decreases from the current gains values, not from the initial ones. when the digital gains reach the initial values, the state machine enters the idle state again. block 0080h = dac a/b block 0280h = dac c/d block 0480h = all dacs fig 20. automute overview block 0080h/0280h/0480h: interface dac dsp - automute lvl_det_sel_xy ign_rf_en_xy sw_mute_xy alarm_clr_xy alarm iqr_err_xy spd_ovf_xy data_iq_valid_xy mds_bsy_xy lvl_det_or_xy temp_alarm_xy ca_err_xy err_rpt_flag_xy clk_mon_xy alarm_cfg_xy hard mute + mute_iq hold mute + mute_iq soft mute + mute_iq soft mute data_invalid_cfg_xy hard mute + mute_iq hold mute + mute_iq soft mute + mute_iq soft mute incident_cfg_xy hard mute + mute_iq hold mute + mute_iq soft mute + mute_iq soft mute direct_cfg_xy hard mute + mute_iq hold mute + mute_iq soft mute + mute_iq soft mute mute_en_xy data invalid direct config incident erf_incident_en_xy spd_incident_en_xy lvl_det_en_xy iqr_incident_en_xy ign_mds_bsy_xy ign_data_invalid_xy hold_data_xy 0 2 3 4 0 234 0 234 0 234 alarm_mrate data_mrate incident_mrate direct_mrate
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 41 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps the mute feature is set by enabling bit mute_en_xy in register mute_ctrl_0_xy . mute events the mute action is triggered by one of the following mute events. each of them is linked to either an error detection, a status change or signal power monitoring: ? spi_sw_mute_xy: software event that can be requested by the host interface through the spi bus. ? rf_en_xy: hardware event that can be requested by the host interface through pins sr_tg_ab and sr_tg_cd. ? clk_mon_xy: event linked to the monitoring of the clocks in the receiver physical layer control block. ? mon_dclk_err_xy: event triggered when a clock error occurs in the cdi . ? ca_err_xy: event triggered when a clock error occurs in the dlp . ? temp_alarm_xy: event triggered when the temperature sensor measures a temperature that exceeds the threshold value. temp_sel_man_xy must be specified first. ? err_rpt_flag_xy: event triggered when data_invalid is detected by the dlp . ? lvl_det_or_xy: fig 21. auto-mute state machine normal operating mode digital gains are equal to initial values one of the ? mute events ? is triggered digital gains set to initial values idle demute wait mute ? wait period ? elapsed and ? mute event ? deasserted digital gains to initial values within specified ? mute rate ? digital gains kept at zero during ? wait period ? time digital gains equal zero digital gains decreased to zero within specified ? mute rate ? one of the ? mute events ? is triggered
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 42 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps event triggered when the signal levels exceed the lvl_det_xy on channel x or y. lvl_det_en_xy and lvl_det_xy must be set first . ? mds_bsy_xy: event triggered while the mds process is busy aligning the dac . ? data_iq_valid_xy: event is triggered when data_invalid is detected by the dlp ? spd_ovf_xy: event triggered when the signal power detector (spd) average value is exceeding the threshold value . ? iqr_err_xy: event triggered when the iq signal is out of range . the monitoring of these events can also be done using the interrupt process available in the dac165xq . once the interrupt is detected, the host controller (e.g. an fpga) can read back the events flags in registers intr_flags_0_xy and intr_flags_1_xy and determine the actions to be taken. ignore events option set bits ign_rt_en_xy, ign_mds_bsy_xy, and ign_data_v_iq_xy of the mute control register for the mute controller to ignore certain events. mute event categories the mute state is entered when one of the mute events is asserted. four categories of mute events can be distinguished: alarm, data, incident, and direct .
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 43 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps [1] all alarm mute events can be disabled using bit ign_alarm_xy. however, their detection can still be monitored using the inte rrupt module. [2] this bit is not auto-clear. [3] the alarm mute events must be cleared with bit alarm_clr_xy to move from the wait state to the demute state. table 19. mute event categories mute event alarm [1] data incident direct enable disable enable disable enable disable enable disable spi_sw_mute_xy default [2] rf_en_xy default ign_rf_en_xy clk_mon_xy alarm_en_xy[0] [3] mon_dclk_err_xy alarm_en_xy [1] [3] ca_err_xy alarm_en_xy [2] [3] temp_alarm_xy alarm_en_xy [3] [3] err_rpt_flag alarm_en_xy [4] [3] default erf_incident_en_xy lvl_det_or_xy alarm_en_xy [5] [3] mds_bsy_xy alarm_en_xy [6] [3] ign_mds_bsy_xy default ign_mds_bsy_xy data_iq_valid alarm_en_xy [7] [3] ign_data_v_iq_xy default ign_data_v_iq_xy spd_ovf_xy alarm_en_xy [8] [3] spd_incident_en_xy iqr_err_xy alarm_en_xy [9] [3] iqr_incident_en_xy
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 44 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps priority between categories the priority in which the auto-mute module evaluates its inputs is: ? priority 1: direct ? priority 2: alarm ? priority 3: data ? priority 4: incident mute actions four mute actions can be selected for each of the four previous mute event categories. the digital data can also be reset to its default value (bits i_dc_lvl_xy and q_dc_lvl_xy) to avoid disturbances in the fir filters. register mute_ctrl_1_xy : ? hard_mute + mute iq: the digital gains of the dacs are set to zero (within 1 dac clock period). the digital path is filled with the default i and q levels. ? hold_mute + mute iq: the outputs of the dacs are kept to the current value (within 1 dac clock period). the digital path is filled with the default i and q levels. remark: bit hold_data_xy must be enabled for this action. if this bit is not set, the overall hold_mute + mute iq actions are not taken into account. ? soft_mute + mute iq: the digital gains of the dacs are swept down to zero at the mute_rate_ctrl_0_xy value . the digital path is filled with the default i and q levels. ? soft_mute: the outputs of the dacs are swept down to zero at the mute_rate_ctrl_0_xy value . the digital path is kept with the received values. remark: as the dc offsets are applied after the digital gain, the outputs are still impacted by their values, even if a mute action event occurs.
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 45 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps mute rate the time period used to decrease or increase the gains during a mute or demute state is called mute rate. each mute action category has its own mute rate available through the registers alarm_mrate_xy, data_mrate_xy, incident_mrate_xy and direct_mrate_xy. fig 22. mute actions representation 1 0 1 0 1 0 1 0 1 2 sample at the output of the digital at time t 0 t 0 + ? mute_rate ? t 0 + ? mute_rate ? + ? wait_period ? t 0 + ? mute_rate ? + ? wait_period ? + ? mute_rate ? gain control gain control gain control idle idle mute wait demute no mute soft mute hold mute hard mute signals seen at the output of the dac auto-mute state machine dac digital latency sample at the input of the digital at time t 0 sample at the output of the digital at time t 0 glitch signal sent at the input of the dac the ? mute action ? starts at t 0 on the output of the digital a ? mute event ? is detected at t 0 at the input of the digital
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 46 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps mute wait period the wait period time can be calculated with equation 14 : (14) at 1 gsps, this gives a wait period between 8 ns and 527 ? s. demute triggering when the mute action is either a direct, an incident or a data mute action, the wait state is enabled as long as the wait period is not elapsed and the event is not released. when the mute action is an alarm mute action, the wait state is enabled as long as the alarm controller is not reset using bit mc_alarm_clr_xy . 11.2.3.11 digital offset adjustment when the dac165xq analog output is dc connected to the next stage, the digital offset correction (bits dac_x_offset[15:0] and dac_y_offset[15:0]) can be used to adjust the common-mode level at the output of each dac. t able 21 shows the variation range of the digital offset. table 20. mute rate availability through alarm_mrate_xy, data_mrate_xy, incident_mrate_xy, and direct_mrate_xy. dac clock 750 mhz 1 ghz 1.5 ghz period ? 8 (ns) 10.67 8.00 5.33 value mute rate (ns) mute rate (ns) mute rate (ns) 0000 10.67 8.00 5.33 0001 21.34 16.00 10.66 0010 42.68 32.00 21.32 0011 85.36 64.00 42.64 0100 170.72 128.00 85.28 0101 341.44 256.00 170.56 0110 682.88 512.00 341.12 0111 1,365.76 1,024.00 682.24 1000 2,731.52 2,048.00 1,364.48 1001 3,642.47 2,731.00 1,819.53 1010 5,463.04 4 096.00 2,728.96 1011 7,283.61 5,461.00 3,638.39 1100 10,926.08 8,192.00 5,457.92 1101 14,557.88 10,915.00 7,272.12 1110 21,852.16 16,384.00 10,915.84 1111 43,704.32 32,768.00 21,831.68 w ait period mute _ wait _ period 1 + ?? 8dac _ clk _ perio d ? ? =
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 47 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 11.2.4 signal detectors 11.2.4.1 level detector a level detector feature is available at the end of the digital path. it can be enabled using bit lvl_det_en_xy . this feature specifies a signal output range limited (or clipped) to ? 128 ? lvl_det to +128 ? lvl_det around the half full-scale (fs) . if the signal value enters the upper or lower clipping area, it is clipped to +128 ? lvl_det or ? 128 ? lvl_det, respectively). figure 23 shows this behavior. use this feature in combination with the auto-mute feature to avoid unexpected spectral spurs after the clipping of the signal . table 21. digital offset adjustment dac_x_offset[15:0] dac_y_offset[15:0] (two?s complement) offset applied 1000 0000 0000 0000 ? 32768 1000 0000 0000 0001 ? 32767 ... ... 1111 1111 1111 1111 ? 1 0000 0000 0000 0000 0 0000 0000 0000 0001 +1 ... ... 0111 1111 1111 1110 +32766 0111 1111 1111 1111 +32767 fig 23. level detector operation fs/2 lvl_detector +128 x lvl_det -128 x lvl_det fs 0
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 48 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 11.2.4.2 signal power detector (spd) the signal power detector (spd) takes the 7 msbs of the i and q signal to determine the iq power of an iq-pair. averaging is done over the programmable number (2 6 , 2 7 to 2 21 ) of iq-pairs using the spd_win_length register . if the spd_avg bit exceeds the 16-bits threshold value, the spd overflow (spd_ovf) flag becomes active and can invoke a mute action depending on the mute control settings. the spd can have a large response time because of the samples average based algorithm. this must be taken into account at system level. 11.2.4.3 iq range (iqr) table 22. level detector values lvl_det[7:0] peak excursion from full-scale / 2 code output range (binary offset) dbfs value 10log(peak excursion x 2 / 65536) 00h 0 32768 nan ... ... ... 19h 3200 32568 to 35968 ? 10.1 dbfs ... ... ... 80h 16384 16384 to 49152 ? 3 dbfs ... ... ... cbh 25984 6784 to 58752 -1 dbfs ... ... ... ffh 32768 0 to 65536 0 dbfs fig 24. signal power detector 7 msbs of i 7 msbs of q i 2 + q 2 iq power spd_winlength averaging spd_avg spd_threshold spd_ovf to the auto-mute module fig 25. iq range or i q iqr_threshold iqr_err to the auto-mute module range detector range detector
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 49 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps the iq range detector checks if the i and q signal values are within the range specified by register iqr_threshold compared to the center value (= 0 if the data are in 2 complement's representation or 32768 if the data are in binary offset representation): ? iqr_threshold < i ? center value < +iqr_threshold ? iqr_threshold < q ? center value < +iqr_threshold 11.2.5 analog core of the dual dac this section refers to the analog configuration required to set up the dual dac core. the clock and output stages are described as well as the internal registers (block 0020h; see figure 26 ) used to configure the clock tree inside the chip. 11.2.5.1 clocks the dac165xq requires one single differential clock (clkin_p, clkin_n) for the whole device (including the digital data path, the quad dac core and the jesd204b interface). during the reset phase (reset_n asserted), the input clock must be stable and running, ensuring a proper reset of the complete device. clock input external configuration the dac165xq incorporates one differential clock input, clkin_n/clkin_p, with embedded 100 ? differential resistor. the clock input can be lvds but it can also be interfaced with cml. block 0020h = dac a/b block 0220h = dac c/d block 0420h = all dacs fig 26. dac core overview block 0020h/0220h/0420h: dac core clock divider dclk dclk_mon_rst_xy dclk_mon_xy wclk_div_byp_xy wclk_div_sel_xy / 2, / 3, / 4, / 6, / 8 / 12, / 16, / 24 wclk wclk_pon_xy clk_div_byp clkin_p clkin_n dac x dac_x_again dac_x_again_pon dac_x_aux_pon dac_x_aux dac_y_aux__pon dac_y_aux dac_y_again_pon dac_y_again aux. dac dac y aux. dac
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 50 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps on-board phase-locked loop (pll) the dac165xq has a single differential clock input to directly feed the digital and analog clock tree of the device. when using the embedded pll, a reference clock has to be provided at this input. the mixed-signal pll synthesizes the correct internal clocks with very low jitter. the predivider (n) and post-divider (m) can be programmed to divider ratio ranges from 1 to 16. the reference clock to the pll should be 61.44 mhz for optimal pll performance. the dac clock frequency can be calculated with equation 15 : (15) figure 28 shows a conceptual view of the pll. digital control words that control the oscillator frequency determine the output frequency of the pll. clock frequency input range the dac165xq can only operate in two modes: ? direct clocking mode: the input clock frequency is limited to 1500 mhz ? divided clocking mode: the input clock is internally divided by 2. the maximum input frequency is 3 ghz. this mode allows the programming of the group delay feature. fig 27. lvds clock configuration fig 28. pll block diagram 100 lvds clkin_p clkin_n f dac fcw mn ? ---------------- f ? = pfd filters dco frequency control word f i divider n f ref divider m f dac table 23. examples f i (mhz) n f ref (mhz) fcw dco (mhz) m f dac (mhz) 122.88 2 61.44 72 4423.68 3 1474.56 122.88 2 61.44 80 4915.20 5 983.04
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 51 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps clocks internal configuration the following registers must be specified to configure the dac165xq in direct clocking mode : ? the final clock is referred to as the "dac clock". this is the clock that is going directly to the quad dac core and is running at maximum speed. from this dac clock two digital clocks are derived: dclk and wclk. dclk is the digital clock used for all logic related to the digital signal processing (dsp) of the dac. dclk is automatically generated from the registers pon_dac_core_cfg_xy_0, interpolation_xy and cdi_mod. registers dclk_mon and dclk_mon_rst can be used to monitor this automatic generation. this flag can also raise the interrupt feature . wclk is the digital clock used for all logic related to the digital lane processing (dlp) of the input interface. this clock must be enabled by bit wclk_pon_xy . the divider ratio wclk_div_sel_xy must be specified using the following equation: (16) where: ? m stands for the number of dacs used inside the dac165xq (m = 1 or m = 2) ? l stands for the number of serial input lanes used (l = 1, l = 2, or l = 4) ? interpolation_xy stands for the interpolation factor specified in register tx_cfg_xy . t able 24 shows the results for nominal use cases (not exhaustive) table 24. wclk_div selection lmf configuration interpolation ratio wclk/dac clock wclk_div_byp wclk_div_sel 421 / 422 2 1/4 0 010 4 1/8 0 100 8 1/16 0 110 222 2 1/2 0 000 4 1/4 0 010 8 1/8 0 100 124 2 1 1 xxx 4 1/2 0 000 8 1/4 0 010 211 2 1/2 0 000 4 1/4 0 010 8 1/8 0 100 wclk d ac clock - ---------------------------- m l interpolation _ xy ? ?? ---------------------------------------------------------------------------- - =
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 52 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps clock domain interface (cdi) a cdi logic handles the error-free data transition from the wclk clock domain to the dclk domain. it consists of 12 buffers that absorb the phase variation between the two clocks. the reliability of the data transmission depends on the clock-frequency ratios and therefore on the interpolation mode. the cdi must be set in the same mode as the interpolation ratio to be properly configured. this mode is configured with register cdi_ctrl . ideally, buffer number 11 is selected as the reference. if jitter of ? 1 clock cycle is injected between the clocks occurs, the pointer can oscillate between buffers 10 and 0. if more jitter is injected, the range increases to buffers 9 and 1, etc. this buffer position can be monitored using register mon_dclk . the variation of the buffer location could also raise an interrupt (see interrupt section). 11.3 analog quad dac core the dac165xq core consists of two dacs. each of them can be independently set to power-down mode or sleep mode if using the dac in single channel mode is preferred (dac_x_again_pon). table 25. interpolation and cdi modes interpolation cdi mode maximum input data rate (msps) ~1 mode 0 (^2) 750 ? 2 mode 0 (^2) 750 ? 4 mode 1 (^4) 375 ? 8 mode 2 (^8) 187.5 fig 29. concept view of the cdi monitoring 0 1 2 3 4 5 6 7 8 9 10 11 nominal case +1 -1
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 53 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 11.3.1 regulation the dac165xq reference circuitry integrates an internal band gap reference voltage which delivers a 0.7 v reference on the gapout pin. decouple pin gapout using a 100 nf capacitor. the reference current is generated via an external resistor of 560 ? (1 %) connected to vires. figure 30 shows the optimal configuration for temperature drift compensation because the band gap reference voltage can be matched to the voltage across the feedback resistor. the dac current can also be adjusted by applying an external reference voltage to the non-inverting input pin gapout and disabling the internal band gap reference voltage (bit bgap_pon_xy). 11.3.2 full-scale current adjustment the default full-scale current (i o(fs) ) is 20 ma. however, further adjustments, ranging from 8.1 ma to 34 ma, can be made to both dacs independently using the serial interface. the settings applied to dac_x_gain[9:0] define the full-scale current of dac x: (17) the dac_y_gain[9:0] define the full-scale current of dac y: (18) 11.4 analog output 11.4.1 dac1658q: high common-mode output voltage the device has four output channels, each producing two complementary current outputs, which enable the reduction of even-order harmonics and noise. the pins are iouta_p/iouta_n, ioutb_p/ioutb_n, ioutc_p/ioutc_n and ioutd_p/ioutd_n. connect these pins to ground (gnd) using a load resistor rl to the 3.3 v analog power supply (v dda(3v3) ). figure 31 shows the equivalent analog output circuit of one dac. this circuit includes a parallel combination of nmos current sources and associated switches for each segment. fig 30. internal reference configuration 560 (1 %) 100 nf dac current sources array band gap reference gapout a gnd a gnd vires dac i ofs ?? ? a 8100 dac _ x _ gain [9:0] 25, 3 ? + = i ofs ?? ? a 8100 dac _ y _ gain [9:0] 25, 3 ? + =
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 54 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps the cascode source configuration increases the output impedance of the source, which improves the dynamic performance of the dac because there is less distortion. depending on the application, the various stages and the targeted performances, the device can be used for an output level of up to 2 v (p-p). 11.4.2 DAC1653Q: low common-mode output voltage the device has four output channels, each producing two complementary current outputs, which enable the reduction of even-order harmonics and noise. the pins are iouta_p/iouta_n and ioutb_p/ioutb_n, ioutc_p/ioutc_n and ioutd_p/ioutd_n. connect these pins using a load resistor r l to the analog ground (gnd). figure 32 shows the equivalent analog output circuit of one dac. this circuit includes a parallel combination of pmos current sources and associated switches for each segment. fig 31. equivalent analog output circuit r l ioutap/ioutbp ioutan/ioutbn 3.3 v gnd gnd r l 3.3 v fig 32. equivalent analog output circuit 3.3 v or 2.5 v ioutxp ioutxn r l r l gnd
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 55 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 11.5 temperature sensor the dac165xq embeds a temperature sensor to monitor the temperature inside the chip. this module is based on a 6-bit resolution adc clocked at dac_clk / (8 ? ts_clkdiv). the mode of measurements is configurable as a one shot measurement, continuous measurements or continuous measurements with alarm flag held in case of temperature exceeding a preset threshold. in continuous mode, the measurement is done every ts_timer cycles. the temps_lvl specifies the threshold level that is compared with the measured value. if the measured value exceeds the threshold, the temp_alarm flag is set and triggers a mute action . the maximum and minimum temperatures measured are stored in registers temp_maxand temp_min . the current temperature is stored in register temp_actual . once the temp_alarm flag is set, it must be reset using the temp_sens_rst_alarm bit of the temperature sensor control register. the maximum and minimum temperature can also be reset using bits temp_sens_rst_max and temp_sens_rst_min of the temperature sensor control register . the value stored in the maximum, current, and minimum registers represents the output value of the adc. this value must be matched to the real temperature. (19) where: ? ? = fig 33. temperature sensor alarm temp_sens_rst_max temp_sens_rst_min temp_alarm temp_sens_toggle temp_sens_full_range temp_sens_mode one shot meas. continous meas. continous meas. + hold alarm temp_sel_man temp_actual temp_max temp_min temp_sens_pon temperature sensor temp_sens_clk_div temp_sens_timer temp_rst_alarm t ( ? c ?? adc _ value ? =
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 56 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 11.6 multiple devices synchronization (mds); jesd204b subclass i the mds feature enables multiple dac channels to be sampled synchronously and phase coherently to within one dac clock period. this feature is part of the jesd204b standard but the implementation adds some unique features that simplify the pcb design. 11.6.1 non-deterministic latency of a system in a system using multiple dac devices, there are numerous sources of timing uncertainties. figure 34 gives an overview of these uncertainties. the sources of uncertainties are shared between the transmitter device (tx), the receiver devices (rx), the pcb layout and the architectures of the jesd204b system clocks. a single device can detect timing drift and uncertainties, but not at system level. therefore a synchronization process is required to enable the sytem to output the analog signals of all the rx devices in a coherent way. moreover, the system becomes predictable if from one start-up to another one, the overall latency is deterministic. the mds feature of the dac165xq has been implemented in compliance with the jesd204b subclass 1 specification to fulfill these requirements. 11.6.2 jesd204b system clocks there are various system 'clocks' that are used in the jesd204b specification. however, only one of them is seen at system level, the device clock, which is provided to the device. the other clocks are related to the jesd204b standard and are used to assemble/deassemble the data in octets and then in 10b words (see jesd204b standard). figure 35 and t able 26 show the relationship between them. fig 34. timing uncertainties when using multiple dac devices s e r i l a tx d e s e r dlp i l a c d i mds dsp (d ac d i g ) analog dac#1 s e r i l a tx d e s e r dlp i l a c d i mds dsp (d ac d i g ) analog dac#2 sync sync clk clock traces are not of the same lengths states machines and clock tree need to be aligned deserializer elastic buffers add some unknown latency serializer elastic buffers add some unknown latency clocks domain interfaces add some unknown uncertainties traces lengths are not necessary of the same lengths
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 57 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps from a system point of view, the tx and rx must share the same values for the internal clocks but not necessarily the same device clocks. figure 36 and figure 37 show the clocking scheme for an fpga and a dac working in an lmf-s = 421-1 configuration. fig 35. jesd204b system clocks table 26. relationship between various clocks clock name ratio with respect to multi-frame clock comments regarding jesd204b specification multi-frame clock 1 - frame clock ? k ceil(17 / f) ? k ? min(32, floor(1024 / f)) character clock ? f ? k f = 1 to 256 bit clock ? 10 ? f ? k 8b/10b encoding sample clock ? s ? k s = 1 to 32 device clock ? d d is integer d k s f 10 internal multi- frame clock device clock bit clock character (octet) clock frame clock sample clock fig 36. clocking scheme fpga 10 7.5 gbps 750 msps 750 msps f = 1 data clock 750 msps 25 mhz d = 30 dac clock 1.5 ghz interpolation factor = x2 k = 30 s = 1 internal device clock fpga lmfc fpga
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 58 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps as all clocks can be derived from the multi-frame clock (mfc), this clock becomes the reference for a jesd204b system. each device used in the system has its own local version of the mfc. these local version are called local multi-frame clock (lmfc). due to the timing uncertainties the phase relationships between all the device lmfcs are unknown. the goal of mds is to be able to realign all lmfcs in a fixed and accurate way. 11.6.3 sysref clock to align all the lmfcs within the system, a new clock named sysref (system reference) is used. this clock is linked to the multi-frame clock by a ratio r. it is a low frequency signal. however, the edges of the signal must be sharp enough as it is sampled by the device clock. fig 37. clocking scheme dac 10 7.5 gbps 750 msps 750 msps f = 1 data clock 750 msps 25 mhz d = 60 dac clock 1.5 ghz interpolation factor = x2 k = 30 s = 1 internal lmfc dac #1 device clock dac #2 fig 38. sysref clock d k s f 10 r sysref clock multi- frame clock device clock bit clock character (octet) clock frame clock sample clock internal
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 59 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps the sysref signals must be propagated to all the devices of the system. they are used to release the lmfc, so they are all aligned over the devices. the sysref signal is sampled by the device clocks. to ensure that all phases of the signals are aligned at the source, the sysref signals and the device clocks must be generated from the same clock ic. all the jesd204b devices sample the sysref signal with their own device clocks. the edge detection of the sysref signal is used as a system timing reference and the device phase-align their lmfcs to the closest edge of the sysref. to ensure an accurate alignment within all devices, the sysref signal must show the same phase at the input port of all the devices to synchronize. therefore, the trace lengths of the sysref signals must be equal for all the dac devices. as the sysref signal is sampled by the device clock, the minimum setup (t su(min) ) and hold (t h(min) ) time are specified with respect to the device clock timing (see figure 40 ). fig 39. system 10 10 10 fpga 7.5 gbps 7.5 gbps 7.5 gbps 750 msps 750 msps 750 msps 750 msps 750 msps 750 msps data clock 750 mhz data clock 750 mhz data clock 750 mhz f = 1 f = 1 f = 1 s = 1 s = 1 s = 1 internal internal internal k = 30 25 mhz r = 5 r = 5 r = 5 d = 30 d = 60 d = 60 fpga clock 750 mhz sysref clock 5 mhz 25 mhz 25 mhz k = 30 k = 30 dac #1 dac #2 dac clock 1.5 gsps dac clock 1.5 gsps all clocks and sysref signals are generated from the same device
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 60 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps figure 41 shows the lmfcs before and after alignment to the sysref clock. fig 40. timing constraints for the sysref signal sampling edge device clock sysref clock t su(min) t h(min) fig 41. lmfcs before and after alignment to the sysref clock before alignment after alignment device clock dac #1 device clock dac #1 device clock fpga device clock fpga device clock dac #2 device clock dac #2 lmfc dac #1 lmfc dac #1 lmfc dac #2 lmfc dac #2 lmfc fpga lmfc fpga sysref clock
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 61 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 11.6.4 mds implementation the dac165xq mds implementation is based on two modules as described in figure 42 : ? m1 : this module contains the sysref detector that is sampled at the dac clock and the control loop used to create a lmfc mds signal. the control loop is clocked with the digital clock. the digital clock equals dac clock / 8. remark: the dac clock and the device clock can differ when using the clock divider. in this section dac clock is referring to the final clock used to sample the dac cores. ? m2 : this module compares the phase of the lmfc rcv received from the jesd204b digital lane processing to the phase of the lmfc mds and shifts the position of the buffer to align the data path to the lmfc mds . 11.6.4.1 capturing the sysref signal module m1 ensures the capture of the sysref signal at dac clock accuracy. this is done by an early-late detector and a control-loop. the control-loop must capture several sysref edges to deliver an accurate lmfc mds signal to the m2 module. the initialization of the control-loop is triggered by the edge detection of the sysref signal (see figure 43 ). it stands for 30 digital clock cycles, after which the capture process starts. the capture is done during the capture window and is repeated at the end of every control fig 42. modules of mds implementation 0 jesd204b lanes m2 ila data rcv lmfc rcv -128 +128 buffer data aligned comparator m1 sysref dac clock digital clock det control loop lmfc mds dac
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 62 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps loop period until the signal is locked. the sysref edge must occur within the capture window. the capture process must be delayed to match this constraint. this is done by programming the capture delay register. figure 44 shows an example on how to set up the m1 module. the dac165xq requires the following parameters: ? lmfc_period (register x0aa) : period of the lmfc in digital clock cycles (e.g. 8 ? 8 ns) fig 43. capturing the sysref signal sysref initialization control loop kick -off control loop period capture window capture delay control loop lmfc mds lmfc period fig 44. example of how to set up the m1 module 10 internal sysref control loop 8 sysref 7.8125 mhz r = 2 128 ns lmfc 15.625 mhz d = 64 dac clock 1 ghz 64 ns 1 ns k = 32 bit clock 5 gbps charact. clock 500 msps f = 1 s = 1 data clock 500 msps frame clock 500 msps 2 ns 2 ns 8 ns digital clock 125 mhz lmfc mds 128 ns control loop kick-off initialization 30 * 8 ns capture delay capture window < 128 ns 128 ns control loop period 64 ns lmfc period jesd204b configuration for the dac timing diagram related to the m1 module
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 63 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps ? capture_delay (register x0ac) : must be tuned using the following equation: example: the capture delay is expressed in digital clock period (for example 2 ? 8 ns) ? capture window and control loop period : these are specified using mds_win_high and mds_win_low registers (respectively x0a9 and x0a8). they are expressed in digital clock cycles and must be set using the following equations: remark: the capture window must be smaller than the sysref period. at the end of the capture process, the lmfc mds signal is provided to the m2 module and the mds_lock bit of the mds status register is set to 1. if the m1 module cannot lock, the mds_bsy flag is kept high and a mute action can be held . 11.6.4.2 aligning the lmfcs and the data module m2 ensures the phase alignment of the lmfc rcv to the closest lmfc mds edge. the lmfc rcv is issued from the digital lane processing by analyzing the ila sequence using the multi-frames /a/ symbols present. the transmitter (tx) is expected to have its self-synchronization process to the global mfc system . it generates the ila sequence based on the aligned lmfc tx . the total latency of the link is compounded of a fixed value (due to pcb traces, devices internal fixed delays, etc.) and an undeterministic value (due to elastic buffers, clocks domains interface, etc.). by buffering the data and the lmfc rcv after the inter-lane alignment process, the m2 module is capable to adjust the position of the buffer delay to match the recovered lmfc mds . figure 45 shows the alignment process for two links. the two links have two different total latencies but due to the lmfc tx and lmfc mds phase synchronization to the mfc system , the various devices are capable to align to the same mfc system edge in a fixed and deterministic way. initialization capture delay + n sysref period ? = 30 8 ns ? ?? 28 ns ? ?? + 2 128 ns ? = c apture window 2 mds _ win _ high 1 + ?? ? = c ontrol loop period capture window mds _ win _ low 1 ++ =
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 64 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps take special care when selecting the mfc system period. a longer period is better than a short one. in general, the mfc system period must be at least two times the maximum latency between devices to avoid a wrong edge selection as shown in figure 46 . fig 45. multiple devices alignment process r a r a r a r a r a r a r a r a deterministic latency total latency #1 = fixed latency #1 + #1 total latency #2 = fixed latency #2 + #2 tx #1 rx #1 tx #2 rx #2 k28.5 k28.5 k28.5 k28.5 ila ila ila ila lmfc tx #1 lmfc rcv #1 lmfc tx #2 lmfc rcv #2 mfc system = lmfc mds #1 = lmfc mds #2 alignment #1 alignment #2
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 65 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps in some cases, the latency between devices is small, but the edge is wrongly selected due to the closest edge criteria. to avoid this, a lmfc preset delay can be applied on all the lmfc mds signals. it is important that all the dac devices receive the same lmfc preset value. if not the latency is not exactly the same. this parameter is set with the lmfc_prst register expressed in digital clock cycles. this value must be adjusted manually for each newly designed system. fig 46. wrong edge selection r a r a ila r a r a ila rx #1 rx #2 k28.5 k28.5 alignment #1 alignment #1 lmfc rcv #1 lmfc rcv #2 lbd = latency between devices mfc system = lmfc mds #1 = lmfc mds #2
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 66 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 11.6.4.3 monitoring the mds process the buffer adjustment performed using the m1 and m2 modules can be read back using the mds_adj_dly register . bits 7 to 3 of this register represent the coarse delay expressed in digital clock cycles whereas bits 2 to 0 represent the fine adjustment in dac clock cycles. the buffer adjustment has a default value of 80h. 11.6.4.4 adding adjustment offset the dac165xq allows adding an offset on top of the automatic adjustment. this is available via register mds_offset_dly . the offset range is from ? 16 to 15 digital clock cycles. this offset value can be set at the start-up time as well as in at later period. this enables compensating a layout error or adding a specific phase to one dac device. another adjustment delay can be set but only after a first automatic alignment using the manual adjustment delay register mds_man_adj_dly . 11.6.4.5 selecting the sysref input port the dac165xq incorporates two sysref differential ports: sysref_e_p/n (east side of the device) and sysref_w_p/n (west side of the device). one of these ports can be selected as the input for the sysref signal. which port is selected is device dependent. one dac165xq uses the eastern sysref while another dac165xq uses the western sysref (see figure 48 ). a. wrong edge selection b. correct edge selection with the lmfc preset delay fig 47. edge selection r a r a ila r a r a ila rx #1 rx #2 k28.5 k28.5 alignment #1 alignment #2 lmfc rcv #1 lmfc rcv #2 lbd = latency between devices mfc system = lmfc mds #1 = lmfc mds #2 r a r a ila r a r a ila lmfc preset delay rx #1 rx #2 k28.5 k28.5 alignment #1 alignment #2 lmfc rcv #1 lmfc rcv #2 lbd = latency between devices = lmfc mds #1 = lmfc mds #2 mfc system
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 67 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps register mds_east_west is used to select between the east port or the west port. each sysref input buffer has an optional internal differential resistor termination of about 100 ? . this resistor can be enabled with registers mds_sel_east_rt and mds_sel_west_rt . the clock edge (rising/falling) on which the sysref signal is sampled can also be selected using registers mds_sel_fe_east and mds_sel_fe_west . 11.7 interrupts in some cases it may be useful if the host-controller is notified that a certain internal event has taken place by means of an interrupt . the dac165xq includes a simple interrupt (intr) controller for this purpose. the intr-signal can be made available on one of the i/o pins. the polarity is programmable . 11.7.1 events monitored the dac165xq monitors various internal events and indicates their occurrence in the intr_flags_xy registers . the following event can be observed: ? intr_dlp_xy: digital lane processing (dlp) has its own interrupt controller. the result of this slave controller is provided to the main interrupt controller through the intr_dlp_xy bit . ? mds_bsy_xy and mds_bsy_xy: refer to the activity of the mds controller. during the synchronization phase, the mds_busy signal is high, and come low once finished. ? mds_bsy_xy reflects the start of the activity of the mds controller ? mds_bsy_xy reflects the end of the activity of the mds controller ? temp_alarm_xy: fig 48. sysref differential ports 1 18 54 49 48 37 19 36 72 55 sysref generator device sysref_e 1 18 54 6 7 37 19 36 72 55 sysref_w dac device #0 dac device #1
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 68 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps indicates that the temperature measured by the on-chip temperature sensor exceeds the threshold temperature . ? lvl_det_or_xy: indicates that one of the level detectors is enabled. ? ca_err_xy: indicates a dlp clock error. ? clk_mon_xy: indicates a cdi clock error. ? dclk_err_mon_xy: indicates a drift on the dclk as specified by register intr_dclk_mon_range_xy . ? err_rpt_flag_xy: indicates the transmission of error reporting via the syncb interface. ? alarm_state_xy: indicates when an auto-mute event occurs . 11.7.2 enabling interrupts an indication if an 0 ? 1 transition of the corresponding monitor- or error indicator activates the intr-signal can be given using the intr_en_xy registers . the intr_flags_xy registers indicate which of the selected events has invoked the interrupt. when bit intr_rst_xy is set to 1 the flags and the intr-signal are reinitialized. 11.7.3 digital lane processing (dlp) interrupt controller the dlp has its own interrupt controller that reports to the main interrupt controller. this dlp interrupt controller is managed from the spi registers of block x00e0 (see figure 49 ).
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 69 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps block 00e0h = dac a/b block 02e0h = dac c/d block 04e0h = all dacs fig 49. digital lane processing monitoring overview block 00e0h/02e0h/04e0h : rx dlp monitoring ila monitoring ila mon lane 0 ila_mon_l_ln0_xy ila_buff_err_l_ln0_xy decoder lane 0 dec_nit_err_p_ln0_xy dec_disp_err_p_ln0_xy dec_kout_l_ln0_xy dec_kout_l_unexp_ln0_xy k28_7_p_ln0_xy k28_5_p_ln0_xy k28_4_p_ln0_xy k28_3_p_ln0_xy k28_0_p_ln0_xy decoder lane 1 dec_nit_err_p_ln1_xy dec_disp_err_p_ln1_xy dec_kout_l_ln1_xy dec_kout_unexp_l_ln1_xy k28_7_p_ln1_xy k28_5_p_ln1_xy k28_4_p_ln1_xy k28_3_p_ln1_xy k28_0_p_ln1_xy decoder lane 2 dec_nit_err_p_ln2_xy dec_disp_err_p_ln2_xy dec_kout_l_ln2_xy dec_kout_unexp_l_ln2_xy k28_7_p_ln2_xy k28_5_p_ln2_xy k28_4_p_ln2_xy k28_3_p_ln2_xy k28_0_p_ln2_xy decoder lane 3 dec_nit_err_p_ln3_xy dec_disp_err_p_ln3_xy dec_kout_l_ln3_xy dec_kout_unexp_l_ln3_xy k28_7_p_ln3_xy k28_5_p_ln3_xy k28_4_p_ln3_xy k28_3_p_ln3_xy k28_0_p_ln3_xy reset rst_k28_flags_p_ln0_xy rst_k28_flags_p_ln1_xy rst_k28_flags_p_ln2_xy rst_k28_flags_p_ln3_xy rst_kout_unexp_flags_xy rst_kout_flags_xy rst_dsip_err_flags_xy rst_nit_err_flags_xy ila mon lane 1 ila_mon_l_ln1_xy ila_buff_err_l_ln1_xy ila mon lane 2 ila_mon_l_ln2_xy ila_buff_err_l_ln2_xy ila mon lane 3 ila_mon_ln3_xy ila_buff_err_l_ln3_xy 10b/8b decoder monitoring flag counter lane 0 flag_cnt_ln0_xy rst_ctrl_flag_cnt_ln0_xy sel_ctrl_flag_cnt_ln0_xy ser_p_ln0, cm_0, nit_err_p_ln0, disp_err_p_ln0, kout_ln0, kout_unexp_i_ln0, k28_7_p_ln0, k28_5_p_ln0, k28_3_p_ln0, k28_0_p_ln0, flag counter lane 1 flag_cnt_ln1_xy rst_ctrl_flag_cnt_ln1_xy sel_ctrl_flag_cnt_ln1_xy ser_p_ln1, cm_1, nit_err_p_ln1, disp_err_p_ln1, kout_i_ln1, kout_unexp_i_ln1, k28_7_p_ln1, k28_5_p_ln1, k28_3_ln1, k28_0_p_ln1, flag counter lane 2 flag_cnt_ln2_xy rst_ctrl_flag_cnt_ln2_xy sel_ctrl_flag_cnt_ln2_xy ser_p_ln2, cm_2, nit_err_p_ln2, disp_err_p_ln2, kout_i_ln2, kout_unexp_i_ln2, k28_7_p_ln2, k28_5_p_ln2, k28_3_p_ln2, k28_0_p_ln2, flag counter lane 3 flag_cnt_ln3_xy rst_ctrl_flag_cnt_ln3_xy sel_ctrl_flag_cnt_ln3_xy ser_p_ln3, cm_3, nit_err_p_ln3, disp_err_p_ln3, kout_i_ln3, kout_unexp_i_ln3, k28_7_p_ln3, k28_5_p_ln3, k28_3_p_ln3, k28_0_p_ln3, flag counters ser ser_lvl_xy (i/q dc levels used for ser test are specified on page x0a) dlp interrupt intr_rst_xy intr_mod_xy: intr depends on ln0 intr depends on ln1 intr depends on ln2 intr depends on ln3 intr depends on ln0 or ln2 intr depends on ln0 or ln1 or ln2 or ln3 no interrupt ser_mod_xy intr_en_nit_xy intr_en_disp_xy intr_en_kout_xy intr_en_kout_unexp_xy intr_en_k28_7_xy intr_en_k28_5_xy intr_en_k28_3_xy intr_en_misc_xy
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 70 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps as this interrupt controller is dedicated to the jesd204b serial interface the intr_mod_xy bits must be specified according to the lmf configuration used in the system. [1] the lane numbering refers to the logical lanes [2] any mode can also be used for debug purposes. [3] the "hold_flag_cnt_en_xy" feature is explained in . register intr_dlp_xy is reinitialized when the bit intr_rst_xy control is set to logic 1 . the dlp events that can be monitored with the interrupt controller are programmable via register intr_en_xy . those events are related to the lanes specified by the intr_mod_xy bits in register intr_ser_ctrl_xy . they can be enabled by the following bits: ? intr_en_nit_xy: a not-in-table (nit) error has occurred on one of the lanes ? intr_en_disp_xy: a disparity error has occurred on one of the lanes ? intr_en_kout_xy: k control characters have been detetected on one of the lanes ? intr_en_kout_unexp_xy: an unexpected k control character has been detected on one of the lanes ? intr_en_k28_7_xy: a k28.7 symbol has been detected on one of the lanes ? intr_en_k28_5_xy: a k28.5 symbol has been detected on one of the lanes ? intr_en_k28_3_xy: a k28.3 symbol has been detected on one of the lanes ? intr_en_misc_xy: an event related to the intr_misc_en_xy register has occurred register intr_misc_en_xy refers to two kinds of events, mainly for debug purposes: ? lane x has reached the cs_init state ? an error has occurred in the ila alignment process on lane x table 27. intr_mod settings intr_mod_xy interrupt setting [1] nominal lmf use [2] 000 dlp interrupt depends on lane 0 124 001 dlp interrupt depends on lane 1 124 010 dlp interrupt depends on lane 2 124 011 dlp interrupt depends on lane 3 124 100 dlp interrupt depends on lane 0 or lane 2 222 101 dlp interrupt depends on lane 0 or lane 1 or lane 2 or lane 3 421 / 422 110 hold_flag_cnt_en_xy [3] - 111 no interrupt -
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 71 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps when register intr_dlp_xy is invoked, the ?flags? registers must be read to determine which event has occurred: ? an intr_en_nit_xy event is related to the dec_nit_err_p_lnx_xy bits of register dec_flags_xy ? an intr_en_disp_xy event is related to the dec_disp_err_p_lnx_xy bits of register dec_flags_xy ? an intr_en_kout_xy event is related to the dec_kout_l_lnx_xy bits of register kout_flag_xy ? an intr_en_kout_unexp_xy event is related to the dec_kout_unexp_l_lnx_xy bits of register kout_unexp_flag_xy ? an intr_en_k28_7 event is related to the k28_7_lnx bits of register k28_flag ? an intr_en_k28_5 event is related to the k28_5_lnx bits of register k28_flag ? an intr_en_k28_3 event is related to the k28_3_lnx bits of register k28_flag ? an intr_en_misc_xy event is related to the cs_state_lnx_xy bits of register cs_state_ln_xy and the ila_buff_err_lnx_xy bits of register ila_buff_err_xy register all flag bits can be reset using register rst_flags_mon_xy . 11.7.4 jesd204b physical and logical lanes the dac165xq integrates a jesd204b serial interface with a high flexibility of configuration. because of various implementations for jesd204b transmitter devices, a flexible configuration of the physical lanes is required. this configuration allows the lane polarity to invert individually and to arbitrary swap the lane order. identifying the lane numbers can be confusing because of the lane swapping. two terms, physical and logical, are used in this document to explicitly identify the lanes. physical lanes : the dac165xq integrates four jesd204b serial receivers that are referenced via the pinning information (see figure 2 ). the descrambler can be enabled or disabled. fig 50. jesd204b receiver 10b 10b sync_out internal configuration interface logical lanes physical lanes lane configuration extraction des buffering lane0 lane1 lane2 lane3 10b 16b 16b sync and word align 8b 10b/8b decoder 8b 8b 8b 8b 8b 8b descrambler descr_en_xy rx controller ila (inter-lane alignment) swap sa (sample assembly)
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 72 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps ? dac a/b physical lane 0 refers to the signal coming from pins vin_ab_p0 and vin_ab_n0 ? dac_a/b physical lane 1 refers to the signal coming from pins vin_ab_p1 and vin_ab_n1 ? dac a/b physical lane 2 refers to the signal coming from pins vin_ab_p2 and vin_ab_n2 ? dac a/b physical lane 3 refers to the signal coming from pins vin_ab_p3 and vin_ab_n3 ? dac c/d physical lane 0 refers to the signal coming from pins vin_cd_p0 and vin_cd_n0 ? dac c/d physical lane 1 refers to the signal coming from pins vin_cd_p1 and vin_cd_n1 ? dac c/d physical lane 2 refers to the signal coming from pins vin_cd_p2 and vin_cd_n2 ? dac c/d physical lane 3 refers to the signal coming from pins vin_cd_p3 and vin_cd_n3 logical lanes : the dac165xq incorporates a swap lanes module (see figure 7 ) that allows a remapping of the lane numbers to be compatible with the system implementation. ? dac a/b logical lane 0 refers to the lane specified with the ln_sel_p_ln0_xy bits in register ln_sel_xy (00cdh) ? dac a/b logical lane 1 refers to the lane specified with the ln_sel_p_ln1_xy bits in register ln_sel_xy (00cdh) ? dac a/b logical lane 2 refers to the lane specified with the ln_sel_p_ln2_xy bits in register ln_sel_xy (00cdh) ? dac a/b logical lane 3 refers to the lane specified with the ln_sel_p_ln3_xy bits in register ln_sel_xy (00cdh) ? dac c/d logical lane 0 refers to the lane specified with the ln_sel_p_ln0_xy bits in register ln_sel_xy (02cdh) ? dac c/d logical lane 1 refers to the lane specified with the ln_sel_p_ln1_xy bits in register ln_sel_xy (02cdh) ? dac c/d logical lane 2 refers to the lane specified with the ln_sel_p_ln2_xy bits in register ln_sel_xy (02cdh) ? dac c/d logical lane 3 refers to the lane specified with the ln_sel_p_ln3_xy bits in register ln_sel_xy (02cdh) the following naming convention are used to distinguish between the physical lanes and the logical lanes in the spi registers: ?p_lnx? is used to identify the physical lanes. ?l_lnx? is used to identify the logical lanes. ?x? stands for the lane number in both cases.
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 73 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 11.7.5 rx digital lane processing (dlp) digital lane processing is the module containing all jesd204b interface controls except the phy deserializer. figure 51 shows the registers for the configuration of the digital lane processing. 11.7.5.1 lane polarity each physical lane polarity can be individually inverted with the pol_p_lnx_xy bits of register p_ln_pol_xy . using this feature transforms the 10 bits from abcdefghij to abcdefghij. 11.7.5.2 lane clocking edge each physical lane can be sampled either by the rising edge or the falling edge of the internal clocking system. this is accomplished by asserting/deasserting the sel_rf_f10_p_lnx_xy bits of register ca_ctrl_xy . block 00c0h = dac a/b block 02c0h = dac c/d block 04c0h = all dacs fig 51. rx digital lane processing overview l sample assembly soft reset ila sr_ila_xy sel_lock_xy: ila starts after all lanes locked ila starts after one of the lanes is locked ila starts after all lane 0 locked ila starts after all lane 1 locked ila starts after all lane 2 locked ila starts after all lane 3 locked dyn_align_en_xy error handling en_kout_unexp_lnx_xy en_nit_err_lnx_xy ign_err_xy block 00c0h/02c0h/04c0h: rx digital lane processing lane polarity pol_p_ln0_xy ila ila lane 0 init_ila_buff_pntr_l_ln0_xy reinit_ila_l_ln0_xy resync_olink_l_ln0_xy sync_pol_xy sel_sync_xy sel_reinit_xy sync/reinit sync_init_lvl_xy sync b pol_p_ln1_xy pol_p_ln2_xy pol_p_ln3_xy swap lanes ln_sel_p_ln0_xy ln_sel_p_ln1_xy ln_sel_ln2_xy ln_sel_p_ln3_xy ila lane 1 init_ila_buff_pntr_l_ln1_xy reinit_ila_l_ln1_xy resync_olink_l_ln1_xy ila lane 2 init_ila_buff_pntr_l_ln2_xy reinit_ila_l_ln2_xy resync_olink_l_ln2_xy ila lane 3 init_ila_buff_pntr_l_ln3_xy reinit_ila_l_ln3_xy resync_olink_l_ln3_xy ila_sync_xy descrambler init_descr_p_ln0_xy descr lane 0 init_descr_p_ln1_xy descr lane 1 init_descr_p_ln2_xy descr lane 2 init_descr_p_ln3_xy descr lane 3 descr_en_xy m f l parameters m parameters f parameters
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 74 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 11.7.5.3 scrambling the descrambler is a 16-bit parallel self-synchronous descrambler based on the polynomial 1 + x 14 + x 15 . from the jesd204b specification, the scrambling/descrambling process only occurs on the user data, not on the code group synchronization or the ila sequence. after two received bytes, the descrambler is correctly set up to decode the data in the proper way. however, it the initial state of the descrambler bits is set incorrectly, the two first decoded bytes are decoded incorrectly. the jesd204b specification proposes an initial state for both scrambler and descrambler to avoid this. using registers init_descr_p_lnx_xy any kind of intitial state can be set in the dac165xq. the descrambling process starts when the ila sequence has finished. this process can be turned off by deasserting bit descr_en_xy in register ila_ctrl_1_xy . 11.7.5.4 lane swapping and selection if the physical lanes do not match with the ordering of the transmitter lanes, they can be reordered using the lane swapping module. as the dac165xq allows various lmf configurations , it is important that the lane swapping respects the following reordering constraints linked to the l value (see t able 28 ). the selection of the logical lanes can be is specified by the ln_sel_l_lnx_xy bits of register ln_sel_xy . t able 29 shows the possible choices regarding the value of the l parameter. table 28. logical lanes versus l values l value logical lanes used for the sample assembly module binary decimal dac a/b 100 4 logical lane 0 logical lane 1 logical lane 2 logical lane 3 010 2 logical lane 0 logical lane 2 001 1 logical lane 0 dac c/d 100 4 logical lane 0 logical lane 1 logical lane 2 logical lane 3 010 2 logical lane 0 logical lane 2 001 1 logical lane 0
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 75 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps table 29. lane mapping between logical and physical lanes regarding the l value l 4 2 1 dac a/b logical lane 0 physical lane 0 physical lane 0 physical lane 0 or or or physical lane 1 physical lane 1 physical lane 1 or or or physical lane 2 physical lane 2 physical lane 2 or or or physical lane 3 physical lane 3 physical lane 3 logical lane 1 physical lane 0 not used not used or physical lane 1 or physical lane 2 or physical lane 3 logical lane 2 physical lane 0 physical lane 0 not used or or physical lane 1 physical lane 1 or or physical lane 2 physical lane 2 or or physical lane 3 physical lane 3 logical lane 3 physical lane 0 not used not used or physical lane 1 or physical lane 2 or physical lane 3
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 76 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 11.7.5.5 word locking and code group synchronization (cgs) when the bits are received from the rx physical layer, dlp has to identify the msb and lsb boundaries of the 10-bit codes from the bitstream. this can be monitored using the lock_cnt_mon_ln01_xy and lock_cnt_mon_ln23_xy registers . when all lanes are locked, the values of the registers are stable and the code group synchronization process can start. this process is described by the jesd204b specification and is represented by the state machine shown in figure 52 . dac c/d logical lane 0 physical lane 0 physical lane 0 physical lane 0 or or or physical lane 1 physical lane 1 physical lane 1 or or or physical lane 2 physical lane 2 physical lane 2 or or or physical lane 3 physical lane 3 physical lane 3 logical lane 1 physical lane 0 not used not used or physical lane 1 or physical lane 2 or physical lane 3 logical lane 2 physical lane 0 physical lane 0 not used or or physical lane 1 physical lane 1 or or physical lane 2 physical lane 2 or or physical lane 3 physical lane 3 logical lane 3 physical lane 0 not used not used or physical lane 1 or physical lane 2 or physical lane 3 table 29. lane mapping between logical and physical lanes regarding the l value l 4 2 1
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 77 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps the cgs states of each lane can be monitored using the csync_state_p_lnx_xy bits of register csync_state_lnx_xy . the definition of each state can be found in t able 30 . 11.7.5.6 sync configuration the sync signal is the feedback signal that is sent to the transmitter device to ensure the jesd204b link synchronization. when all lanes are in csync_init state a synchronization request is sent to the sync buffer that is linked to pins sync_outp and sync_outn (see figure 2 ). the polarity of this buffer is controlled by bit sync_pol_xy of register syncout_mod_xy . by default the sync_request is active low. the sync_request signal can be specified by bits sel_sync and sync_init_lvl of register syncout_mod_xy register. bit sync_init_lvl_xy of register syncout_mod_xy only specifies the state of the sync_request signal after resetting the cgs state machine (at start-up time or after device reset only). fig 52. code group synchronization table 30. code group synchronization state machine csync_state_lnn[1:0] name definition 00 csync_init looking for k28_5 (/k/) symbol 01 csync_chck four consecutive k28_5 (/k/) symbols have been received 10 csync_data code group synchronization achieved reset/start-up sync_init_lvl sync_request while receiving less than 4 consecutive valid k28.5 symbols while receiving valid symbols while receiving less than 4 consecutive valid symbols or after receiving 3 invalid symbols after receiving 4 consecutive valid k28.5 symbols after receiving 4 consecutive valid symbols after receiving 1 invalid symbol after receiving 3 invalid symbols cs_check cs_init cs_data table 31. sync_request control sel_sync[2:0] description 000 sync_request active when state machine of one of the lanes is in cs_init mode 001 sync_request active when state machine of all lanes is in cs_init mode 010 sync_request active when state machine of lane 0 is in cs_init mode 011 sync_request active when state machine of lane 1 is in cs_init mode
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 78 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 11.7.5.7 inter-lane alignment this module handles the alignment of the logical lanes based on the ila sequence described in the jesd204b specification. inter-lane alignment starts when all lanes are locked and at reception of the first non-k28.5 (or /k/) symbol. during the ila sequence, the k28.3 (/a/ symbol) is used to align the data streams. during this sequence, the length (k) of the multi-frame is measured. this value is used by the lane monitoring and correction process. the value is also used for the mds circuitry, where the sysref signal is expected to be a multiplication of the multi-frame length (k) in the jesd204b specification. during the second multi-frame, the jesd204b configuration data of each physical lane is stored in register blocks x0120 and x0140 (see figure 53 ). the dac165xq does not do anything with these configuration data. they are only made available for the host controller. 100 sync_request active when state machine of lane 2 is in cs_init mode 101 sync_request active when state machine of lane 3 is in cs_init mode 110 sync_request fixed to 1 111 sync_request fixed to 0 table 31. sync_request control ?continued sel_sync[2:0] description fig 53. jesd204 read configuration for physical lanes overview block nnn0h: jesd204 read configuration (dac x/y) config 0 p_ln_did p_ln_scr p_ln_f p_ln_m p_ln_cs p_ln_sbclss_vs p_ln_jesd_vs p_ln_hd p_ln_res1 p_ln_res2 p_ln_fchk p_ln_l p_ln_k p_ln_n p_ln_n p_ln_s p_ln_cf p_ln_adj_cnt p_ln_bid p_ln_lid p_ln_adj_dir p_ln_adj_ph config 1 jesd204 configuration config 2 config 3 config 4 config 5 config 6 config 7 config 8 config 9 config 10 config 11 config 12 config 13
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 79 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps the inter-lane alignment synchronization is enabled by default, but it can be disabled using bit ila_sync_xy of register ila_ctrl_1_xy register . when ila is disabled, the lane-alignment can be done manually using registers man_align_p_ln_1_0_xy . the manual mode must first be enabled using bit force_align_xy of register force_align_xy . the ila module uses a 16-bit buffer for each lane. the first /a/ symbol received over the lanes is used as reference. the /a/ symbols of the other lanes, which are received later, are compared to the first one to be all aligned. the initial location of the symbols is predefined by the init_ila_buff_pntr_l_ln01_xy and init_ila_buff_pntr_l_ln23_xy registers . the alignment can be monitored with the ila_mon_l_lnn_xy bits of the ila_mon_l_ln10 and ila_mon_l_ln32 registers . if the lane difference is too great, a buffer out of range error occurs, which can be monitored with bits ila_buff_err_l_lnx_xy of the ila_buff_err_xy register . in this specific case, a reinitialization of the full link can be requested by setting the reinit_ila_l_lnx_xy bits of the reinit_ctrl_xy register. the jesd204b specification also mentions a dynamic realignment mode where a monitoring process is checking the /a/-symbol location. this can realign the data stream if two successive /a/ symbols are found at the same new position. by default this monitoring and correction process is disabled to avoid any moving latency over the link, but one can enable the feature by setting bit dyn_align_en_xy of the force_align_xy register . 11.7.5.8 character replacement character replacement, as specified by the jesd204b specification, can occur at the end of the frame (k28.7 or /f/ symbol) or at the end of the multi-frame (k28.3 or /a/ symbol). by default this feature is enabled, but it can be disabled using bit frame_align_en_xy of the force _lock register . remark: the dac165xq can handle multi-frame length values (k) between and 32 but with the restriction that the number of octets in a multi-frame must always be even. this implies that if f = 1, a value of k = 17 is not allowed. when f = 1 only even values > 17 are allowed. working with f = 1 and k = 17 often implies that the character replacement process is not reliable. 11.7.5.9 sample assembly sample assembly handles the assembly of the data based on the lmf parameters described by the lmf_ctrl register . the following configurations are supported: ? lmf = 421 ? lmf = 422 ? lmf = 222 table 32. overview of generic parts of register addresses dac a/b dac c/d lane 0 nnn = 012 nnn = 032 lane 1 nnn = 013 nnn = 033 lane 2 nnn = 014 nnn = 034 lane 3 nnn = 015 nnn = 035 ceil 17 f ? ??
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 80 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps ? lmf = 124 sample assembly is based on the logical lanes definition when updating the l value . 11.7.5.10 resynchronization over links the dac165xq recognizes a k28.5 (/k/) symbols sequence coming over its lanes. this identification allows resynchronization of the device if the resync_olink_l_lnx_xy bits of register reinit_ctrl_xy are set correctly . 11.7.5.11 symbols detection monitoring and error handling the dlp decodes the 10-bit words to 8-bit words. the decoding table is specified in the ieee 802.3-2005 specification. during decoding, the disparity is calculated according to the disparity rules mentioned in the same specification. the jesd204b specification also defines the following definitions: ? valid: the code group is found in the column of the 10b/8b decoding tables according to the current running disparity. ? disparity error: the received code group exists in the 10b/8b decoding table, but is not found in the correct column according to the current running disparity. ? not-in-table (nit) error: the received code group is not found in the 10b/8b decoding table of either disparity. ? invalid: a code group that either shows a disparity error or that does not exist in the 10b/8b decoding table. the not-in-table error (nit) and disparity error (disp) can be monitored using bits dec_nit_err_p_lnx_xy and dec_disp_err_p_lnx_xy of the dec_flags_xy register . both are considered invalid, but the dac165xq has some flexibility in this definition. using the nad_err_corr bit of the err_hndlng register either nit errors only or nit errors and disparity errors can be set as invalid. moreover, the specified invalid errors can also be totally ignored by setting the bit ign_err_xy of the err_hndlng register to logic 1 . this specific mode is designed for debug purposes only, especially when sample error measurement needs to be executed. the valid/invalid status of the decoded word can trigger the mute feature using bits data_v_iq_cfg_xy of the mute_ctrl_1_xy register . the following comma symbols are detected during data transmission irrespective of the running disparity: /k/ = k28.5 /f/ = k28.7 /a/ = k28.3 /r/ = k28.0 /q/ = k28.4 their single detection is monitored in registers kout_flag_xy and k28_flag_xy (.
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 81 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps during the data transmission phase, only k28.3 (/a/) and k28.7 (/f/) symbols are expected. sometimes (e.g. wrong bit transmission), a code group is interpreted as a k character that is not k28.3 or k28.7. if this occurs a kout_unexp flag is asserted that can be read using bits dec_kout_unexp_l_lnx_xy of the kout_unexp_flag_xy (. all the previous flags can be reset using the rst_flags_mon_xy register . detection of them can also assert the dlp interrupt . 11.7.6 monitoring and test modes the dac165xq embeds various monitoring and test modes that are useful during the prototyping phase of a system. remark: the test capability linked to observing specific characters, errors or state machine statuses is not reviewed in this section. it is up to the reader to define specific modes based on the dac165xq capability. 11.7.6.1 flag counters due to the high data rate of the jesd204b serial interface, it is hard to monitor events that occur on the lanes in real time. four multi-purpose counters have been added to the design to help this monitoring. each counter is 16 bits wide and is linked to one lane. it increments its value each time a specific event occurs. these flags counters can be read using the flag_cnt_lnx_xy registers and reset using the rst_ctrl_flag_cnt_lnx_xy bits of the ctrl_flag_cnt_lnxx registers the flag counters can also be reset automatically when dlp is reset by setting the auto_rst_flag_cnts_xy bit of register rst_buff_err_flags to logic 1. the specification of the event that increments the counter is done by setting the sel_ctrl_flags_cnt_lnxx_xy bits of the ctrl_flag_cnt_lnxx_xy registers to one of the sources described in t able 33 . when the counter is reaching its maximum value (0xffff), this value is held until the next counter reset. bit hold_flag_cnt_en_xy of the rst_buff_err_flags_xy register gives two options for when a counter reaches the maximum value. table 33. counter source default settings are shown highlighted. sel_cfc_lnn[2:0] source 000 not-in-table error 001 disparity error 010 k symbol not found 011 unexpected k symbol found 100 k28_7 (/f/) symbol found 101 k28_5 (/k/) symbol found 110 k28_3 (/a/) symbol found 111 k28_0 (/r/) symbol found
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 82 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps when the counters are stopped, an interrupt can be activated . this feature makes it possible to, for instance, analyze the occurrence of character replacement or nit errors. 11.7.6.2 sample error rate (ser) a sample error rate feature is implemented in the dac165xq to analyze the quality of the transmission. due to the 8b10b encoding, the analysis is done at sample level only and not at bit level. the transmitter sends a constant data over the link and the dac165xq compared this received value to the value specified in the ser_lvl_xy_lsb and ser_lvl_xy_msb registers . enable the scrambling on both transmitter and receiver side to add more random effect on the data. the ser_lvl_xy_msb and ser_lvl_xy_lsb are specifying a 16-bit value at the lane level, it means the device can be considered as operating in one of two modes: ? f = 2 mode: the lane is receiving 16-bit data specified by ser_lvl_xy_msb and ser_lvl_xy_lsb. ? f = 1 mode: the lane is receiving alternately 8-bit data specified by ser_lvl_xy_msb and ser_lvl_xy_lsb. the ser mode requires that the dac is already synchronized (using cgs and ila sequence). the kick-off of the measurement is done by setting the ser_mod_xy bit of register ser_intr_ctrl_xy . in this mode, the flags counters are used to count the number of 16-bit samples that do not match the ser_lvl_xy value. this mode enables the establishing of the sample error rate of each lane. 11.7.6.3 jtspat test the jitter tolerance scrambled pattern (jtspat) is an 1180-bit pattern intended for receiving jitter tolerance testing for scrambled systems. the jtspat test pattern consists of two copies of jspat and an additional 18 characters intended to cause extreme late and early phases in the cdr pll followed by a sequence, which can cause an error (i.e. an isolated bit following a long run). this pattern was developed to stress the receiver within the boundary conditions established by scrambling. table 34. hold_flag_cnt_en_xy options default settings are shown highlighted. hold_flag_cnt_en_xy option 0 all counters are independent. each counter continues its own counting. 1 all counters are linked. when one counter reached the maximum value and stops, all other counters stop as well.
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 83 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps [1] this table must be read, starting from the top, left-to-right first and then line-by-line to follow the sequence. the dac165xq embeds a jtspat checker. the control registers are located in the jesd204 receiver monitoring registers block . table 35. jitter tolerance scrambled pattern symbols sequence [1] d1.4 0111010010 d16.2 0110110101 d24.7 0011001110 d30.4 1000011101 d9.6 1001010110 d10.5 0101011010 d16.2 1001000101 d7.7 1110001110 d24.0 0011001011 d13.3 1011000011 d23.4 0001011101 d13.2 1011000101 d13.7 1011001000 d1.4 0111010010 d7.6 1110000110 d0.2 1001110101 d21.5 1010101010 d22.1 0110101001 d23.4 0001011101 d20.0 0010110100 d27.1 1101101001 d30.7 1000011110 d17.7 1000110001 d4.3 1101010011 d6.6 0110010110 d23.5 0001011010 d7.3 1110001100 d19.3 1100101100 d27.5 110101010 d19.3 1100100011 d5.3 1010010011 d22.1 0110101001 d5.0 1010010100 d15.5 0101111010 d24.7 0011001110 d16.3 1001001100 d1.2 0111010101 d23.5 0001011010 d29.2 1011100101 d31.1 0101001001 d10.4 0101011101 d4.2 0010100101 d5.5 1010011010 d10.2 0101010101 d21.5 1010101010 d10.2 0101010101 d21.5 1010101010 d20.7 0010110111 d11.7 1101001000 d20.7 0010110111 d18.7 0100110001 d29.0 1011100100 d16.6 0110110110 d25.3 1001100011 d1.0 1000101011 d18.1 0100111001 d30.5 1000011010 d5.2 1010010101 d21.6 1010100110 d1.4 0111010010 d16.2 0110110101 d24.7 0011001110 d30.4 1000011101 d9.6 1001010110 d10.5 0101011010 d16.2 1001000101 d7.7 1110001110 d24.0 0011001011 d13.3 1011000011 d23.4 001011101 d13.2 1011000101 d13.7 1011001000 d1.4 0111010010 d7.6 1110000110 d0.2 1001110101 d21.5 1010101010 d22.1 0110101001 d23.4 0001011101 d20.0 0010110100 d27.1 1101101001 d30.7 1000011110 d17.7 1000110001 d4.3 1101010011 d6.6 0110010110 d23.5 0001011010 d7.3 1110001100 d19.3 1100101100 d27.5 1101101010 d19.3 1100100011 d5.3 1010010011 d22.1 0110101001 d5.0 1010010100 d15.5 0101111010 d24.7 0011001110 d16.3 1001001100 d1.2 0111010101 d23.5 0001011010 d27.3 1101100011 d3.0 1100010100 d3.7 1100011110 d14.7 0111001000 d28.3 0011101100 d30.3 0111100011 d30.3 1000011100 d7.7 1110001110 d7.7 0001110001 d20.7 0010110111 d11.7 1101001000 d20.7 0010110111 d8.7 0100110001 d29.0 1011100100 d16.6 0110110110 d25.3 1001100011 d1.0 1000101011 d18.1 0100111001 d30.5 1000011010 d5.2 1010010101 d21.6 1010100110
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 84 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 11.7.6.4 dlp strobe the data coming out of the ila module can be sampled by setting the dlp_strobe_xy bit of the misc_ctrl register . on each lane two octets are stored, which can be read out through registers p_lnxx_smpl_msb and p_lnxx_smpl_lsb . the selection of the lane to read out the data is done by registers p_ln10_sel and p_ln32_sel . 11.7.7 io-mux the dac165xq uses two general purpose pins, io0 and io3. io0 is always an output. io1 can be configured as an input or as an output by setting the io_en bit of the ehs_ctrl register . when acting as an output, the two io pins are multiplexed to internal signals that can be useful for debug purposes. t able 36 shows the main configuration when using bits io_sel_x of the io_mux_ctrl_x register. the definitions of the three registers depend of the "indicator" and the "range" values used to specify the signal that is sent through pins io0 and io1 (see tables below). 11.7.8 dlp latency the variable delay (latency uncertainty) is the result of uncertainties and variation in design implementations along the path between the transmit logic device and the dac165xq. the inter-lane alignment (ila) module present in digital layer processing (dlp) realigns the input streams to the last data received. table 36. definition of io_sel registers register name b7 b6 b5 b4 b3 b2 b1 b0 io_sel_4 io3 indicator[1:0] io2 indicator[1:0] io1 indicator[1:0] io0 indicator[1:0] io_sel_3 io3 range[7:0] io_sel_2 io2 range[7:0] io_sel_1 io1 range[7:0] io_sel_0 io0 range[7:0] table 37. output signals for combination of indicators and ranges indicator[1:0] range[7:0] output signal 00 xxxx xxx0 io0: wclk io1: dclk 00 xxxx 0011 synchronization 10 1111 0000 end of ila 10 1111 0001 end of ila 11 1100 0000 interrupt 11 1100 0001 interrupt 11 1111 even io0: fixed to logic 1 io1: fixed to logic 0 11 1111 odd io0: fixed to logic 0 io1: fixed to logic 1
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 85 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps [1] d = garantueed by design. [2] wclk clock cycle. 11.8 jesd204b phy receiver each jesd204b lane owns its own physical deserializer (rx phy) that provides the 10-bit data stream to the dlp module. the spi registers of block x0160 control the various features of the rx phy, like the equalizer, the common-mode voltage and the resistor termination. the registers of block 0180h monitor the status of these controls. remark: most of the main controls (power on/off, pll clock dividers,etc.) are automatically set while specyfing the lmf mode and/or by the main_ctrl register . table 38. digital layer processing latency symbol parameter conditions test [1] min typ max unit t d delay time digital layer processing delay d 11 - 26 cycles [2]
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 86 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 11.8.1 lane input each lane is current mode logic (cml) compliant. the common-mode voltage and the termination resistor can be programmed using register hs_rx_rt_vcm_xy and registers hs_rx_lnx_rt_ref_size_xy (0x12 to 0x16). when not used, the lane input buffer can be set to a high impedance mode (register hs_rx_rt_ctrl_xy;). blocks 0160h/0180h = dac a/b blocks 0360h/0380h = dac c/d blocks 0560h/0580h = all dacs fig 54. rx phy control overview v cm registers followed by a * could be read back at the same position (address and bits) in block 0220h to check the validation of the controlled action. 10.n m hs_rx_cdr_divn_xy hs_rx_cdr_divm_xy hs_rx_cdr_low_speed_en_xy references hs_rx_rt_vcm_sel_xy* hs_rx_rt_vcm_ref_xy* sync b sync_set_vcm_xy sync_set_lvl_xy equalizer hs_rx_ln0_eqz_if_gain_xy hs_rx_ln0_rt_en_xy* hs_rx_ln0_rt_hiz_en_xy* hs_rx_eqz_auto_zero_en_xy hs_rx_ln0_eqz_en_xy auto_zero vin_ab_p0/ vin_cd_p0 vin_ab_n0/ vin_cd_n0 block 0160h/0360h/0560h: rx phy / block 0180h/0380h/0580h: rx phy monitoring * resistor termination hs_rx_ln0_rt_ref_size_xy vin_ab_p1/ vin_cd_p1 vin_ab_n1/ vin_cd_n1 vin_ab_p2/ vin_cd_p2 vin_ab_n2/ vin_cd_n2 sync_en_xy vin_ab_p3/ vin_cd_p3 vin_ab_n3/ vin_cd_n3 v cm equalizer hs_rx_ln1_eqz_if_gain_xy hs_rx_ln1_rt_en_xy* hs_rx_ln1_rt_hiz_en_xy* hs_rx_ln1_eqz_en_xy auto_zero resistor termination hs_rx_ln1_rt_ref_size_xy v cm equalizer hs_rx_ln2_eqz_if_gain_xy hs_rx_ln2_rt_en_xy* hs_rx_ln2_rt_hiz_en_xy* hs_rx_ln2_eqz_en_xy auto_zero resistor termination hs_rx_ln2_rt_ref_size_xy v cm equalizer hs_rx_ln3_eqz_if_gain_xy hs_rx_ln3_rt_en_xy* hs_rx_ln3_rt_hiz_en_xy* hs_rx_ln3_eqz_en_xy auto_zero resistor termination hs_rx_ln3_rt_ref_size_xy dclk (see block 0040h)
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 87 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps ac-coupling is always required (see figure 55 ). 11.8.2 equalizer the dac165xq embeds an internal equalizer (bits hs_rx_lnx_eqz_en_xy in register hs_rx_eqz_ctrl_xy) in each high-speed serial lane. this improves the interference robustness between signals by amplifying the high-frequency jumps in the data conserving the energy of the low-frequencies ones. the equalizer can be programmed depending on the quality of the channel used (pcb traces/layout, connectors, etc.). the auto-zero feature (bit hs_rx_eqz_auto_zero_en_xy in register hs_rx_eqz_ctrl_xy) is enabled by default for the deserializer to adapt itself to the common-mode of the received signal. this feature can be set manually. it uses an external algorithm that controls the dac165xq via the spi bus. set two gains to control the high-frequency and low-frequency jumps of the data (bits hs_rx_lnx_eq_if_gain_xy[2:0] of register hs_rx_lnx_eqz_gain_xy). 11.8.3 deserializer the deserializer performs the incoming data clock recovery and also the serial-to-parallel conversion. one global pll provides the same reference clock to the four lanes. the pll configuration is automatically done when specifying the lmf parameters (see t able 10 ). when using the dac165xq with a low serial input data rate (lower than 1.5 gbps), it is recommended to enable the low speed mode of the clock data recovery (cdr) unit by setting the hs_rx_cdr_ls_en_xy bit of register hs_rx_cdr_divx_xy . 11.8.4 phy test mode a special test mode is available for measurement purposes only. the recovered clock of each cdr unit can be transmitted to the sync buffer after a frequency division by 20. this is done by setting bit sync_tst_data_en_xy of register sync_sel_ctrl to logic 1 . bit sync_tst_data_sel_xy is used to specify which cdr clock is used. fig 55. ac-coupling 50 50 50 50 z diff = 100 v dd1 v dd2 d ata in + d ata in ?
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 88 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 11.9 output interfacing configuration 11.9.1 dac1658q: high common-mode output voltage 11.9.1.1 basic output configuration using a differentially coupled transformer output provides optimum distortion performance. in addition, it helps to match the impedance and provides electrical isolation. the dac1658q can generate a differential output of 1 v (p-p). in this configuration, connect the center tap of the transformer to a 25 ? resistor, which is connected to the 3.3 v analog power supply. this adjusts the dc common-mode to around 3.05 v (see figure 56 ). 11.9.1.2 low input impedance iq-modulator interface the dac1658q can be easily connected to low input impedance iq-modulators. the image of the local oscillator can be canceled using the digital offset control in the device. figure 57 shows an example of a connection between the dac1658q and a low input impedance modulator. fig 56. 1 v (p-p) differential output with transformer 50 2:1 50 ioutx_p dac iouta_p/iouta_n ioutb_p/ioutb_n v o(cm) = 3.05 v v o(dif) = 1 v ioutx_n 3.3 v 25 50 3.3 v 3.3 v 0 ma to 20 ma 0 ma to 20 ma
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 89 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 11.9.1.3 iq-modulator - dc interface when the system operation requires to keep the dc component of the spectrum, the dac1658q can use a dc interface to connect an iq-modulator. in this case, the image of the local oscillator can be canceled using the digital offset control in the device. figure 58 shows an example of a connection to an iq modulator with a 1.7 v common input level. (1) if r int = 100 ? , then r ext = not connected (2) if r int = 200 ? , then r ext = 200 ? fig 57. dac1658q with low input impedance iq-modulator interface iouta_p/ioutb_p 3.3 v dac iq modulator r int = 100 /200 50 r ext r int 50 iouta_n/ioutb_n auxa_p/auxb_p auxa_n/auxb_n bba_p/bbb_p bba_n/bbb_n 0 ma to 20 ma low pass filter iouta_p/iouta_n ioutb_p/ioutb_n v o(cm) = 2.7 v v o(dif) = 1 v fig 58. iq-modulator: dc interface with a 1.7 v common input level iouta_p/ioutb_p 5 v dac 68 54.9 54.9 68 84.5 84.5 iouta_n/ioutb_n bba_p/bbb_p bba_p/bba_n bbb_p/bbb_n v i(cm) = 1.7 v v i(dif) = 0.92 v iouta_p/iouta_n ioutb_p/ioutb_n v o(cm) = 2.78 v v o(dif) = 1.52 v iq modulator (v i(cm) = 1.7 v) bba_n/bbb_n 0 ma to 20 ma 100 low pass filter
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 90 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps figure 59 shows an example of a connection to an iq-modulator with a 3.3 v common input level. 11.9.2 DAC1653Q: low common-mode output voltage 11.9.2.1 basic output configuration using a differentially coupled transformer output provides optimum distortion performance. in addition, it helps to match the impedance and provides electrical isolation. the DAC1653Q can generate a differential output of 1 v (p-p). in this configuration, connect the center tap of the transformer to a 25 ? resistor, which is connected to the gnd. this adjusts the dc common-mode to around 0.25 v (see figure 56 ). 11.9.2.2 low input impedance iq-modulator interface the DAC1653Q can be easily connected to low input impedance iq-modulators. the image of the local oscillator can be canceled using the digital offset control in the device. figure 57 shows an example of a connection between the DAC1653Q and a low input impedance modulator. fig 59. iq-modulator: dc interface with a 3.3 v common input level iouta_p/ioutb_p 5 v dac 64.9 15 15 64.9 205 205 iouta_n/ioutb_n auxa_p/auxb_p auxa_n/auxb_n bba_p/bbb_p bba_p/bba_n bbb_p/bbb_n v i(cm) = 3.3 v v i(dif) = 0.93 v iouta_p/iouta_n ioutb_p/ioutb_n v o(cm) = 2.9 v v o(dif) = 1.43 v iq modulator (v i(cm) = 3.3 v) bba_n/bbb_n 0 ma to 20 ma 100 low pass filter
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 91 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 11.9.2.3 high input impedance iq-modulator interface the DAC1653Q can be easily connected to high input impedance iq-modulators. the image of the local oscillator can be canceled using the digital offset control in the device. figure 61 shows an example of a connection between the DAC1653Q and a high input impedance modulator. fig 60. low input impedance iq-modulator interface bbp bbn dac 0 to 20 ma low pass filter iq modulator r int = 100 r int r dac r dac r ext r ext ioutxp ioutxn fig 61. high input impedance iq-modulator interface dac ioutxp ioutxn 0 to 20 ma low pass filter iq-modulator r int = r int r dac r dac r ext r ext
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 92 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 11.10 design recommendations 11.10.1 power and grounding use a separate power supply regulator for the generation of the 1.2 v analog power (pins 43, 48. 51. 56) and the 1.2 v digital power (pins 7, 10, 33, 36) to ensure optimal performance. high-speed input lanes are powered by a 1.2 v power supply that can require a dedicated power supply. pins 15, 16, 19, 22, 25, 28 can be connected to either the global 1.2 v power supply or to a dedicated one. also, include individual lc decoupling for the following six sets of power pins: ? v dda(1v2) ldo low noise: ? dac ab (pins 65, 68, 69, 72) ? dac cd (pins 55, 58, 59, 62) ? biasing (pins 50, 53) ? clock (pin 2) ? v dda(3v3) ldo low noise: ? output ab (pins 1, 64) ? output cd (pins 54, 63) ? v dda(3v3) ldo low noise: ? pll (pin 5) ? v ddd(1v2) switch supply: ? digital (pins 8, 15, 40, 47) ? sync output (pin 39) ? jesd204b input (pin 16, 23, 32) ? io/spi (pin 41) use at least two capacitors for each power pin decoupling. locate these capacitors as close as possible to the dac1658q power pins. use a separate ldo for the generation of the 1.2 v analog power (v dda(1v2) ) and the 1.2 v digital power (v ddd(1v2) ) to ensure the best performance. the die pad is used for both the power dissipation and electrical grounding. insert several vias (typically 7 ? 7 to connect the internal ground plane to the top layer die area.
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 93 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 12. package outline fig 62. package outline (qfn72)
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 94 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps fig 63. pcb land pattern
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 95 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 13. abbreviations table 39. abbreviations acronym description b bandwidth bwa broadband wireless access cdi clock domain interface cdma code division multiple access cml current mode logic cmos complementary metal oxide semiconductor dac digital-to-analog converter dsp digital signal processing edge enhanced data rates for gsm evolution fir finite impulse response gsm global system for mobile communications if intermediate frequency imd3 third order intermodulation lmds local multipoint distribution service lo local oscillator lvds low-voltage differential signaling nco numerically controlled oscillator nmos negative metal-oxide semiconductor pll phase-locked loop sfdr spurious-free dynamic range spi serial peripheral interface wcdma wide band code division multiple access wll wireless local loop
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 96 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 14. glossary 14.1 static parameters inl ? the deviation of the transfer function from a best fit straight line (linear regression computation). dnl ? the difference between the ideal and the measured output value between successive dac codes. 14.2 dynamic parameters spurious-free dynamic range (sfdr) ? the ratio between the rms value of the reconstructed output sine wave and the rms value of the largest spurious observed (harmonic and non-harmonic, excluding dc component) in the frequency domain. intermodulation distortion (imd) ? from a dual-tone digital input sine wave (these two frequencies being close together), the intermodulation distortion products imd2 and imd3 (second order and third order components) are defined below. imd2 ? the ratio between the rms value of either tone and the rms value of the worst second order intermodulation product. imd3 ? the ratio between the rms value of either tone and the rms value of the worst third order intermodulation product. total harmonic distortion (thd) ? the ratio between the rms value of the harmonics of the output frequency and the rms value of the output sine wave. usually, the calculation of thd is done on the first 5 harmonics. signal-to-noise ratio (snr) ? the ratio between the rms value of the reconstructed output sine wave and the rms value of the noise excluding the harmonics and the dc component. restricted bandwidth spurious-free dynamic range (sfdr rbw ) ? the ratio between the rms value of the reconstructed output sine wave and the rms value of the noise, including the harmonics, in a given bandwidth centered around f offset .
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 97 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 15. revision history table 40. revision history document id release date data sheet status change notice supersedes DAC1653Q/ dac1658q 1.03 13th, may 2013 advance data sheet - -
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 98 of 101 continued >> integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 16. tables table 1. ordering information . . . . . . . . . . . . . . . . . . . . .3 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 table 3. limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 4. thermal characteristics . . . . . . . . . . . . . . . . . . .8 table 5. characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 6. specific characteristics . . . . . . . . . . . . . . . . . .12 table 7. dynamic characteristics dac165xq1g50 . . . .15 table 8. dynamic characteristics dac165xq1g25 . . . .17 table 9. dynamic characteristics dac16qxd1g . . . . .19 table 10. lmf configuration if dac165xq configures in dual jeds204b links . . . . . . . . . . . . . . . . . . . . . . . .24 table 11. read mode or write mode access description 28 table 12. double buffered registers . . . . . . . . . . . . . . . .29 table 13. spi timing characteristics . . . . . . . . . . . . . . . .31 table 14. interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 15: interpolation filter coefficients . . . . . . . . . . . . .34 table 16. complex modulator operation mode . . . . . . . .36 table 17. inversion filter coefficients . . . . . . . . . . . . . . . .38 table 18. dac transfer function . . . . . . . . . . . . . . . . . . .39 table 19. mute event categories . . . . . . . . . . . . . . . . . . .43 table 20. mute rate availability . . . . . . . . . . . . . . . . . . . .46 table 21. digital offset adjustment . . . . . . . . . . . . . . . . .47 table 22. level detector values . . . . . . . . . . . . . . . . . . . .48 table 23. examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 24. wclk_div selection . . . . . . . . . . . . . . . . . . . .51 table 25. interpolation and cdi modes . . . . . . . . . . . . . .52 table 26. relationship between various clocks . . . . . . . .57 table 27. intr_mod settings . . . . . . . . . . . . . . . . . . . . .70 table 28. logical lanes versus l values . . . . . . . . . . . . .74 table 29. lane mapping between logical and physical lanes regarding the l value . . . . . . . . . . . . . . . . . . . .75 table 30. code group synchronization state machine . . .77 table 31. sync_request control . . . . . . . . . . . . . . . . . . . .77 table 32. overview of generic parts of register addresses . 79 table 33. counter source . . . . . . . . . . . . . . . . . . . . . . . .81 table 34. hold_flag_cnt_en_xy options . . . . . . . .82 table 35. jitter tolerance scrambled pattern symbols sequence [1] . . . . . . . . . . . . . . . . . . . . . . . . . . .83 table 36. definition of io_sel registers . . . . . . . . . . . . .84 table 37. output signals for combination of indicators and ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 table 38. digital layer processing latency . . . . . . . . . . . .85 table 39. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .95 table 40. revision history . . . . . . . . . . . . . . . . . . . . . . . .97
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 99 of 101 continued >> integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 thermal characteristics. . . . . . . . . . . . . . . . . . . 8 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 9 9.1 common characteristics . . . . . . . . . . . . . . . . . . 9 9.2 specific characteristics . . . . . . . . . . . . . . . . . . 12 10 dynamic characteristics . . . . . . . . . . . . . . . . . 15 11 application information. . . . . . . . . . . . . . . . . . 23 11.1 general description. . . . . . . . . . . . . . . . . . . . . 23 11.2 device operation. . . . . . . . . . . . . . . . . . . . . . . 26 11.2.1 spi configuration block . . . . . . . . . . . . . . . . . . 27 11.2.1.1 protocol description . . . . . . . . . . . . . . . . . . . . 27 11.2.1.2 spi controller configuration. . . . . . . . . . . . . . . 28 11.2.1.3 double buffering and transfer mode . . . . . . . 29 11.2.1.4 device description . . . . . . . . . . . . . . . . . . . . . 30 11.2.1.5 spi timing description . . . . . . . . . . . . . . . . . . . 30 11.2.2 main device configuration . . . . . . . . . . . . . . . . 31 11.2.3 interface dac dsp block . . . . . . . . . . . . . . . . 32 11.2.3.1 input data format. . . . . . . . . . . . . . . . . . . . . . . 32 11.2.3.2 finite impulse response (fir) filters . . . . . . . 32 11.2.3.3 single sideband modulator (ssbm). . . . . . . . 35 11.2.3.4 40-bit nco . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11.2.3.5 nco low power. . . . . . . . . . . . . . . . . . . . . . . . 37 11.2.3.6 inverse sinx / x. . . . . . . . . . . . . . . . . . . . . . . . 37 11.2.3.7 minus 3db. . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11.2.3.8 phase correction. . . . . . . . . . . . . . . . . . . . . . . 38 11.2.3.9 digital gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11.2.3.10 auto-mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.2.3.11 digital offset adjustment . . . . . . . . . . . . . . . . . 46 11.2.4 signal detectors . . . . . . . . . . . . . . . . . . . . . . . 47 11.2.4.1 level detector . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.2.4.2 signal power detector (spd) . . . . . . . . . . . . . 48 11.2.4.3 iq range (iqr). . . . . . . . . . . . . . . . . . . . . . . . 48 11.2.5 analog core of the dual dac . . . . . . . . . . . . . 49 11.2.5.1 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.3 analog quad dac core . . . . . . . . . . . . . . . . . . 52 11.3.1 regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.3.2 full-scale current adjustment . . . . . . . . . . . . . 53 11.4 analog output . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.4.1 dac1658q: high common-mode output voltage. 53 11.4.2 DAC1653Q: low common-mode output voltage . 54 11.5 temperature sensor . . . . . . . . . . . . . . . . . . . . 55 11.6 multiple devices synchronization (mds); jesd204b subclass i. . . . . . . . . . . . . . . . . . . 56 11.6.1 non-deterministic latency of a system . . . . . . 56 11.6.2 jesd204b system clocks . . . . . . . . . . . . . . . 56 11.6.3 sysref clock . . . . . . . . . . . . . . . . . . . . . . . . 58 11.6.4 mds implementation . . . . . . . . . . . . . . . . . . . 61 11.6.4.1 capturing the sysref signal . . . . . . . . . . . . 61 11.6.4.2 aligning the lmfcs and the data . . . . . . . . . . 63 11.6.4.3 monitoring the mds process . . . . . . . . . . . . . 66 11.6.4.4 adding adjustment offset . . . . . . . . . . . . . . . . 66 11.6.4.5 selecting the sysref input port . . . . . . . . . . 66 11.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11.7.1 events monitored . . . . . . . . . . . . . . . . . . . . . . 67 11.7.2 enabling interrupts . . . . . . . . . . . . . . . . . . . . . 68 11.7.3 digital lane processing (dlp) interrupt controller 68 11.7.4 jesd204b physical and logical lanes . . . . . . 71 11.7.5 rx digital lane processing (dlp) . . . . . . . . 73 11.7.5.1 lane polarity. . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.7.5.2 lane clocking edge . . . . . . . . . . . . . . . . . . . . 73 11.7.5.3 scrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.7.5.4 lane swapping and selection. . . . . . . . . . . . . 74 11.7.5.5 word locking and code group synchronization (cgs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11.7.5.6 sync configuration . . . . . . . . . . . . . . . . . . . . 77 11.7.5.7 inter-lane alignment . . . . . . . . . . . . . . . . . . . . 78 11.7.5.8 character replacement. . . . . . . . . . . . . . . . . . 79 11.7.5.9 sample assembly. . . . . . . . . . . . . . . . . . . . . . 79 11.7.5.10 resynchronization over links . . . . . . . . . . . . 80 11.7.5.11 symbols detection monitoring and error handling 80 11.7.6 monitoring and test modes. . . . . . . . . . . . . . . 81 11.7.6.1 flag counters . . . . . . . . . . . . . . . . . . . . . . . . . 81 11.7.6.2 sample error rate (ser). . . . . . . . . . . . . . . . 82 11.7.6.3 jtspat test . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.7.6.4 dlp strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 11.7.7 io-mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 11.7.8 dlp latency . . . . . . . . . . . . . . . . . . . . . . . . . . 84 11.8 jesd204b phy receiver . . . . . . . . . . . . . . . . 85 11.8.1 lane input . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 11.8.2 equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 11.8.3 deserializer . . . . . . . . . . . . . . . . . . . . . . . . . . 87 11.8.4 phy test mode . . . . . . . . . . . . . . . . . . . . . . . . 87
integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specifications de scribed herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without noti ce. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suit ability of idt?s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written a greement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright, 2013. all rights reserved. 11.9 output interfacing configuration . . . . . . . . . . . 88 11.9.1 dac1658q: high common-mode output voltage . 88 11.9.1.1 basic output configuration . . . . . . . . . . . . . . . 88 11.9.1.2 low input impedance iq-modulator interface . 88 11.9.1.3 iq-modulator - dc interface . . . . . . . . . . . . . . 89 11.9.2 DAC1653Q: low common-mode output voltage . 90 11.9.2.1 basic output configuration . . . . . . . . . . . . . . . 90 11.9.2.2 low input impedance iq-modulator interface . 90 11.9.2.3 high input impedance iq-modulator interface 91 11.10 design recommendations . . . . . . . . . . . . . . . . 92 11.10.1 power and grounding . . . . . . . . . . . . . . . . . . . 92 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 93 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 95 14 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 14.1 static parameters . . . . . . . . . . . . . . . . . . . . . . 96 14.2 dynamic parameters. . . . . . . . . . . . . . . . . . . . 96 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . 97 16 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 13 abbreviations 205 14 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 14.1 static parameters . . . . . . . . . . . . . . . . . . . . . 206 14.2 dynamic parameters. . . . . . . . . . . . . . . . . . . 206 15 revision history . . . . . . . . . . . . . . . . . . . . . . . 207 16 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
DAC1653Q/dac1658q ? idt 2013. all rights reserved. advance data sheet rev. 1.03 ? 13 may 2013 101 of 101 integrated device technology DAC1653Q/dac1658q quad 16-bit dac: 10 gbps jesd204b interface; up to 1.50 gsps

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